From: Sandeep Maheswaram <sanm@codeaurora.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Felipe Balbi <balbi@kernel.org>,
Stephen Boyd <swboyd@chromium.org>,
Doug Anderson <dianders@chromium.org>,
Matthias Kaehlcke <mka@chromium.org>
Cc: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Manu Gautam <mgautam@codeaurora.org>,
Chandana Kishori Chiluveru <cchiluve@codeaurora.org>,
Sandeep Maheswaram <sanm@codeaurora.org>
Subject: [PATCH v7 2/4] usb: dwc3: qcom: Add interconnect support in dwc3 driver
Date: Wed, 1 Apr 2020 10:45:43 +0530 [thread overview]
Message-ID: <1585718145-29537-3-git-send-email-sanm@codeaurora.org> (raw)
In-Reply-To: <1585718145-29537-1-git-send-email-sanm@codeaurora.org>
Add interconnect support in dwc3-qcom driver to vote for bus
bandwidth.
This requires for two different paths - from USB master to
DDR slave. The other is from APPS master to USB slave.
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Signed-off-by: Chandana Kishori Chiluveru <cchiluve@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
---
drivers/usb/dwc3/dwc3-qcom.c | 128 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 126 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index 1dfd024..d33ae86 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -13,6 +13,7 @@
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/extcon.h>
+#include <linux/interconnect.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/phy/phy.h>
@@ -43,6 +44,14 @@
#define SDM845_QSCRATCH_SIZE 0x400
#define SDM845_DWC3_CORE_SIZE 0xcd00
+/* Interconnect path bandwidths in MBps */
+#define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
+#define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
+#define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000)
+#define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
+#define APPS_USB_AVG_BW 0
+#define APPS_USB_PEAK_BW MBps_to_icc(40)
+
struct dwc3_acpi_pdata {
u32 qscratch_base_offset;
u32 qscratch_base_size;
@@ -76,8 +85,13 @@ struct dwc3_qcom {
enum usb_dr_mode mode;
bool is_suspended;
bool pm_suspended;
+ struct icc_path *usb_ddr_icc_path;
+ struct icc_path *apps_usb_icc_path;
};
+static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom);
+static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom);
+
static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
{
u32 reg;
@@ -239,7 +253,7 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
static int dwc3_qcom_suspend(struct dwc3_qcom *qcom)
{
u32 val;
- int i;
+ int i, ret;
if (qcom->is_suspended)
return 0;
@@ -251,6 +265,10 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom)
for (i = qcom->num_clocks - 1; i >= 0; i--)
clk_disable_unprepare(qcom->clks[i]);
+ ret = dwc3_qcom_interconnect_disable(qcom);
+ if (ret)
+ dev_warn(qcom->dev, "failed to disable interconnect %d\n", ret);
+
qcom->is_suspended = true;
dwc3_qcom_enable_interrupts(qcom);
@@ -276,6 +294,10 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom)
}
}
+ ret = dwc3_qcom_interconnect_enable(qcom);
+ if (ret)
+ dev_warn(qcom->dev, "failed to enable interconnect %d\n", ret);
+
/* Clear existing events from PHY related to L2 in/out */
dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
@@ -285,6 +307,101 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom)
return 0;
}
+
+/**
+ * dwc3_qcom_interconnect_init() - Get interconnect path handles
+ * @qcom: Pointer to the concerned usb core.
+ *
+ */
+static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
+{
+ struct device *dev = qcom->dev;
+ int ret;
+
+ if (!device_is_bound(&qcom->dwc3->dev))
+ return -EPROBE_DEFER;
+
+ qcom->usb_ddr_icc_path = of_icc_get(dev, "usb-ddr");
+ if (IS_ERR(qcom->usb_ddr_icc_path)) {
+ dev_err(dev, "Error: (%ld) failed getting usb-ddr path\n",
+ PTR_ERR(qcom->usb_ddr_icc_path));
+ return PTR_ERR(qcom->usb_ddr_icc_path);
+ }
+
+ qcom->apps_usb_icc_path = of_icc_get(dev, "apps-usb");
+ if (IS_ERR(qcom->apps_usb_icc_path)) {
+ dev_err(dev, "Error: (%ld) failed getting apps-usb path\n",
+ PTR_ERR(qcom->apps_usb_icc_path));
+ return PTR_ERR(qcom->apps_usb_icc_path);
+ }
+
+ ret = dwc3_qcom_interconnect_enable(qcom);
+ if (ret) {
+ dev_err(dev, "failed to enable interconnect %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * dwc3_qcom_interconnect_exit() - Release interconnect path handles
+ * @qcom: Pointer to the concerned usb core.
+ *
+ * This function is used to release interconnect path handle.
+ */
+static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
+{
+ icc_put(qcom->usb_ddr_icc_path);
+ icc_put(qcom->apps_usb_icc_path);
+}
+
+/* Currently we only use bandwidth level, so just "enable" interconnects */
+static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
+{
+ struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
+ int ret;
+
+ if (dwc->maximum_speed == USB_SPEED_SUPER)
+ ret = icc_set_bw(qcom->usb_ddr_icc_path,
+ USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
+ else
+ ret = icc_set_bw(qcom->usb_ddr_icc_path,
+ USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
+
+ if (ret)
+ return ret;
+
+ ret = icc_set_bw(qcom->apps_usb_icc_path,
+ APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
+ if (ret)
+ icc_set_bw(qcom->usb_ddr_icc_path, 0, 0);
+
+ return ret;
+}
+
+/* To disable an interconnect, we just set its bandwidth to 0 */
+static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
+{
+ int ret;
+
+ ret = icc_set_bw(qcom->usb_ddr_icc_path, 0, 0);
+ if (ret)
+ return ret;
+
+ ret = icc_set_bw(qcom->apps_usb_icc_path, 0, 0);
+ if (ret)
+ goto err_reenable_memory_path;
+
+ return 0;
+
+ /* Re-enable things in the event of an error */
+err_reenable_memory_path:
+ dwc3_qcom_interconnect_enable(qcom);
+
+ return ret;
+}
+
static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data)
{
struct dwc3_qcom *qcom = data;
@@ -648,6 +765,10 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
goto depopulate;
}
+ ret = dwc3_qcom_interconnect_init(qcom);
+ if (ret)
+ goto depopulate;
+
qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
/* enable vbus override for device mode */
@@ -657,7 +778,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
/* register extcon to override sw_vbus on Vbus change later */
ret = dwc3_qcom_register_extcon(qcom);
if (ret)
- goto depopulate;
+ goto interconnect_exit;
device_init_wakeup(&pdev->dev, 1);
qcom->is_suspended = false;
@@ -667,6 +788,8 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
return 0;
+interconnect_exit:
+ dwc3_qcom_interconnect_exit(qcom);
depopulate:
if (np)
of_platform_depopulate(&pdev->dev);
@@ -697,6 +820,7 @@ static int dwc3_qcom_remove(struct platform_device *pdev)
}
qcom->num_clocks = 0;
+ dwc3_qcom_interconnect_exit(qcom);
reset_control_assert(qcom->resets);
pm_runtime_allow(dev);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2020-04-01 5:17 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-01 5:15 [PATCH v7 0/4] ADD interconnect support for Qualcomm DWC3 driver Sandeep Maheswaram
2020-04-01 5:15 ` [PATCH v7 1/4] dt-bindings: usb: qcom,dwc3: Introduce interconnect properties " Sandeep Maheswaram
2020-04-14 15:22 ` Rob Herring
2020-04-14 20:30 ` Stephen Boyd
2020-04-01 5:15 ` Sandeep Maheswaram [this message]
2020-05-14 11:29 ` [PATCH v7 2/4] usb: dwc3: qcom: Add interconnect support in dwc3 driver Felipe Balbi
2020-05-14 11:30 ` Felipe Balbi
2020-05-14 17:13 ` Matthias Kaehlcke
2020-05-14 21:02 ` Georgi Djakov
2020-05-15 3:57 ` Viresh Kumar
2020-05-15 4:23 ` Manu Gautam
2020-05-15 4:26 ` Viresh Kumar
2020-05-15 5:54 ` Felipe Balbi
2020-05-15 6:11 ` Georgi Djakov
2020-05-15 6:29 ` Felipe Balbi
2020-05-18 18:35 ` Bjorn Andersson
2020-05-19 3:29 ` Viresh Kumar
2020-05-26 11:04 ` Sandeep Maheswaram (Temp)
2020-05-26 11:34 ` Georgi Djakov
2020-05-26 11:43 ` Felipe Balbi
2020-05-28 9:24 ` Sandeep Maheswaram (Temp)
2020-06-03 17:36 ` Stephen Boyd
2020-06-04 9:43 ` Sandeep Maheswaram (Temp)
2020-06-04 11:16 ` Stephen Boyd
2020-06-15 19:42 ` Matthias Kaehlcke
2020-06-16 4:52 ` Sandeep Maheswaram (Temp)
2020-06-16 20:38 ` Matthias Kaehlcke
2020-06-30 22:42 ` Matthias Kaehlcke
2020-07-07 5:11 ` Sandeep Maheswaram (Temp)
2020-07-07 15:52 ` Matthias Kaehlcke
2020-04-01 5:15 ` [PATCH v7 3/4] arm64: dts: qcom: sdm845: Add interconnect properties for USB Sandeep Maheswaram
2020-04-14 20:31 ` Stephen Boyd
2020-04-01 5:15 ` [PATCH v7 4/4] arm64: dts: qcom: sc7180: " Sandeep Maheswaram
2020-04-14 20:32 ` Stephen Boyd
2020-04-29 18:35 ` [PATCH v7 0/4] ADD interconnect support for Qualcomm DWC3 driver Matthias Kaehlcke
2020-05-08 6:29 ` Sandeep Maheswaram (Temp)
2020-05-14 10:49 ` Felipe Balbi
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