[PATCH] x86/cpufeatures: Add enumeration for serialize instruction

From: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
To: Ingo Molnar <mingo@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Borislav Petkov <bp@suse.de>
Cc: linux-kernel@vger.kernel.org,
	Ricardo Neri <ricardo.neri@intel.com>,
	Ricardo Neri <ricardo.neri-calderon@linux.intel.com>,
	x86@kernel.org, "Ravi V. Shankar" <ravi.v.shankar@intel.com>
Subject: [PATCH] x86/cpufeatures: Add enumeration for serialize instruction
Date: Thu,  2 Apr 2020 18:40:26 -0700	[thread overview]
Message-ID: <20200403014026.19137-1-ricardo.neri-calderon@linux.intel.com> (raw)

The serialize instruction ensures that before the next instruction is
fetched and executed, all the modifications to flags, registers, and memory
made by previous instructions are completed, draining all buffered writes
to memory.

Importantly, the serialize instruction does not modify registers,
arithmetic flags or memory.

Hence, the serialize instructions provides a better way for software
to serialize execution than using instructions such as cpuid, which does
modify registers and, in virtual machines, causes a VM exit.

This instruction is supported by the CPU if CPUID.7H.EDX[bit 14] is
set.

Cc: x86@kernel.org
Cc: "Ravi V. Shankar" <ravi.v.shankar@intel.com>
Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
---
This new instruction is documented in the latest version of the Intel
Architecture Instruction Set Extensions and Future Features Programming
Reference Chapter 2.1 located at
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index db189945e9b0..cd9b1ec022ec 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -364,6 +364,7 @@
 #define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */
 #define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */
 #define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */
+#define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
 #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
 #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */
 #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */
-- 
2.17.1

