From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: <skomatineni@nvidia.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <frankc@nvidia.com>, <hverkuil@xs4all.nl>,
<sakari.ailus@iki.fi>, <helen.koike@collabora.com>
Cc: <digetx@gmail.com>, <sboyd@kernel.org>,
<linux-media@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-clk@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: [RFC PATCH v6 5/9] dt-binding: tegra: Add VI and CSI bindings
Date: Fri, 3 Apr 2020 18:25:03 -0700 [thread overview]
Message-ID: <1585963507-12610-6-git-send-email-skomatineni@nvidia.com> (raw)
In-Reply-To: <1585963507-12610-1-git-send-email-skomatineni@nvidia.com>
Tegra contains VI controller which can support up to 6 MIPI CSI
camera sensors.
Each Tegra CSI port from CSI unit can be one-to-one mapper to
VI channel and can capture from an external camera sensor or
from built-in test pattern generator.
This patch adds dt-bindings for Tegra VI and CSI.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
.../display/tegra/nvidia,tegra20-host1x.txt | 73 ++++++++++++++++++----
1 file changed, 60 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
index 9999255..4731921 100644
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
@@ -40,14 +40,30 @@ of the following host1x client modules:
Required properties:
- compatible: "nvidia,tegra<chip>-vi"
- - reg: Physical base address and length of the controller's registers.
+ - reg: Physical base address and length of the controller registers.
- interrupts: The interrupt outputs from the controller.
- - clocks: Must contain one entry, for the module clock.
+ - clocks: clocks: Must contain one entry, for the module clock.
See ../clocks/clock-bindings.txt for details.
- - resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
- - reset-names: Must include the following entries:
- - vi
+ - Tegra20/Tegra30/Tegra114/Tegra124:
+ - resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+ - reset-names: Must include the following entries:
+ - vi
+ - Tegra210:
+ - power-domains: Must include venc powergate node as vi is in VE partition.
+ - Tegra210 has CSI part of VI sharing same host interface and register space.
+ So, VI device node should have CSI child node.
+
+ - csi: mipi csi interface to vi
+
+ Required properties:
+ - compatible: "nvidia,tegra210-csi"
+ - reg: Physical base address offset to parent and length of the controller
+ registers.
+ - clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks.
+ See ../clocks/clock-bindings.txt for details.
+ - power-domains: Must include sor powergate node as csicil is in
+ SOR partition.
- epp: encoder pre-processor
@@ -309,13 +325,44 @@ Example:
reset-names = "mpe";
};
- vi {
- compatible = "nvidia,tegra20-vi";
- reg = <0x54080000 0x00040000>;
- interrupts = <0 69 0x04>;
- clocks = <&tegra_car TEGRA20_CLK_VI>;
- resets = <&tegra_car 100>;
- reset-names = "vi";
+ vi@54080000 {
+ compatible = "nvidia,tegra210-vi";
+ reg = <0x0 0x54080000 0x0 0x700>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
+
+ clocks = <&tegra_car TEGRA210_CLK_VI>;
+ power-domains = <&pd_venc>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0x0 0x0 0x54080000 0x2000>;
+
+ csi@838 {
+ compatible = "nvidia,tegra210-csi";
+ reg = <0x838 0x1300>;
+ assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
+ <&tegra_car TEGRA210_CLK_CILCD>,
+ <&tegra_car TEGRA210_CLK_CILE>,
+ <&tegra_car TEGRA210_CLK_CSI_TPG>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
+ <&tegra_car TEGRA210_CLK_PLL_P>,
+ <&tegra_car TEGRA210_CLK_PLL_P>;
+ assigned-clock-rates = <102000000>,
+ <102000000>,
+ <102000000>,
+ <972000000>;
+
+ clocks = <&tegra_car TEGRA210_CLK_CSI>,
+ <&tegra_car TEGRA210_CLK_CILAB>,
+ <&tegra_car TEGRA210_CLK_CILCD>,
+ <&tegra_car TEGRA210_CLK_CILE>,
+ <&tegra_car TEGRA210_CLK_CSI_TPG>;
+ clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
+ power-domains = <&pd_sor>;
+ };
};
epp {
--
2.7.4
next prev parent reply other threads:[~2020-04-04 1:25 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-04 1:24 [RFC PATCH v6 0/9] Add Tegra driver for video capture Sowjanya Komatineni
2020-04-04 1:24 ` [RFC PATCH v6 1/9] arm64: tegra: Fix sor powergate clocks and reset Sowjanya Komatineni
2020-04-04 1:25 ` [RFC PATCH v6 2/9] arm64: tegra: Add reset-cells to mc Sowjanya Komatineni
2020-04-04 1:25 ` [RFC PATCH v6 3/9] dt-bindings: clock: tegra: Add clk id for CSI TPG clock Sowjanya Komatineni
2020-04-14 18:12 ` Rob Herring
2020-04-04 1:25 ` [RFC PATCH v6 4/9] clk: tegra: Add Tegra210 CSI TPG clock gate Sowjanya Komatineni
2020-04-04 1:25 ` Sowjanya Komatineni [this message]
2020-04-14 18:14 ` [RFC PATCH v6 5/9] dt-binding: tegra: Add VI and CSI bindings Rob Herring
2020-04-04 1:25 ` [RFC PATCH v6 6/9] media: tegra: Add Tegra210 Video input driver Sowjanya Komatineni
2020-04-05 19:37 ` Dmitry Osipenko
2020-04-06 18:58 ` Sowjanya Komatineni
2020-04-05 19:45 ` Dmitry Osipenko
2020-04-05 19:57 ` Dmitry Osipenko
2020-04-05 19:51 ` Dmitry Osipenko
2020-04-05 20:35 ` Dmitry Osipenko
2020-04-06 15:35 ` Sowjanya Komatineni
2020-04-06 16:05 ` Dmitry Osipenko
2020-04-06 16:12 ` Sowjanya Komatineni
2020-04-06 16:29 ` Dmitry Osipenko
2020-04-06 16:37 ` Sowjanya Komatineni
2020-04-06 17:02 ` Sowjanya Komatineni
2020-04-06 19:53 ` Dmitry Osipenko
2020-04-06 20:05 ` Sowjanya Komatineni
2020-04-06 20:28 ` Dmitry Osipenko
2020-04-06 20:30 ` Sowjanya Komatineni
2020-04-05 20:54 ` Dmitry Osipenko
2020-04-05 21:11 ` Dmitry Osipenko
2020-04-06 15:41 ` Sowjanya Komatineni
2020-04-06 16:11 ` Dmitry Osipenko
2020-04-07 19:05 ` Sowjanya Komatineni
2020-04-06 19:48 ` Dmitry Osipenko
2020-04-06 20:00 ` Sowjanya Komatineni
2020-04-06 20:02 ` Dmitry Osipenko
2020-04-06 20:20 ` Sowjanya Komatineni
2020-04-06 20:37 ` Dmitry Osipenko
2020-04-06 20:38 ` Sowjanya Komatineni
2020-04-06 20:43 ` Sowjanya Komatineni
2020-04-06 20:54 ` Dmitry Osipenko
2020-04-06 21:18 ` Sowjanya Komatineni
2020-04-06 20:45 ` Dmitry Osipenko
2020-04-06 20:50 ` Sowjanya Komatineni
2020-04-06 20:53 ` Dmitry Osipenko
2020-04-06 20:55 ` Sowjanya Komatineni
2020-04-06 20:56 ` Dmitry Osipenko
2020-04-06 21:02 ` Sowjanya Komatineni
2020-04-06 21:11 ` Dmitry Osipenko
2020-04-06 21:15 ` Sowjanya Komatineni
2020-04-06 21:39 ` Sowjanya Komatineni
2020-04-06 22:00 ` Sowjanya Komatineni
2020-04-06 22:07 ` Sowjanya Komatineni
2020-04-06 23:18 ` Dmitry Osipenko
2020-04-06 23:48 ` Sowjanya Komatineni
2020-04-06 23:50 ` Sowjanya Komatineni
2020-04-07 21:08 ` Sowjanya Komatineni
2020-04-07 22:08 ` Dmitry Osipenko
2020-04-07 22:14 ` Dmitry Osipenko
2020-04-07 22:22 ` Sowjanya Komatineni
2020-04-07 23:12 ` Dmitry Osipenko
[not found] ` <1a31cd60-739f-0660-1c45-31487d2f2128@nvidia.com>
2020-04-07 23:38 ` Sowjanya Komatineni
2020-04-07 23:56 ` Sowjanya Komatineni
2020-04-07 23:57 ` Sowjanya Komatineni
2020-04-07 23:59 ` Sowjanya Komatineni
2020-04-08 0:00 ` Sowjanya Komatineni
2020-04-08 14:21 ` Dmitry Osipenko
2020-04-08 17:45 ` Sowjanya Komatineni
2020-04-08 18:58 ` Sowjanya Komatineni
2020-04-08 19:38 ` Sowjanya Komatineni
2020-04-09 3:38 ` Sowjanya Komatineni
2020-04-09 14:50 ` Dmitry Osipenko
2020-04-09 18:28 ` Sowjanya Komatineni
2020-04-10 18:47 ` Dmitry Osipenko
2020-04-10 18:59 ` Sowjanya Komatineni
2020-04-10 19:45 ` Dmitry Osipenko
2020-04-07 19:39 ` Dmitry Osipenko
2020-04-07 19:42 ` Sowjanya Komatineni
2020-04-10 19:47 ` Dmitry Osipenko
2020-04-04 1:25 ` [RFC PATCH v6 7/9] MAINTAINERS: Add Tegra Video driver section Sowjanya Komatineni
2020-04-04 1:25 ` [RFC PATCH v6 8/9] dt-bindings: reset: Add ID for Tegra210 VI reset Sowjanya Komatineni
2020-04-14 18:14 ` Rob Herring
2020-04-04 1:25 ` [RFC PATCH v6 9/9] arm64: tegra: Add Tegra VI CSI support in device tree Sowjanya Komatineni
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