From: Dinh Nguyen <dinguyen@kernel.org>
To: linux-clk@vger.kernel.org
Cc: dinguyen@kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, sboyd@kernel.org,
mturquette@baylibre.com, robh+dt@kernel.org,
mark.rutland@arm.com
Subject: [PATCHv6 2/5] clk: socfpga: remove clk_ops enable/disable methods
Date: Mon, 6 Apr 2020 11:04:15 -0500 [thread overview]
Message-ID: <20200406160418.27476-3-dinguyen@kernel.org> (raw)
In-Reply-To: <20200406160418.27476-1-dinguyen@kernel.org>
The enable/disable clock ops are already defined in the standard clock
ops, so we don't need to assign them.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v6: no changes
v5: no changes
v4: no changes
v3: no changes
v2: created
---
drivers/clk/socfpga/clk-pll-a10.c | 2 --
drivers/clk/socfpga/clk-pll-s10.c | 2 --
drivers/clk/socfpga/clk-pll.c | 2 --
3 files changed, 6 deletions(-)
diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c
index 3816fc04b274..6d9395106c0c 100644
--- a/drivers/clk/socfpga/clk-pll-a10.c
+++ b/drivers/clk/socfpga/clk-pll-a10.c
@@ -102,8 +102,6 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node,
pll_clk->hw.hw.init = &init;
pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
- clk_pll_ops.enable = clk_gate_ops.enable;
- clk_pll_ops.disable = clk_gate_ops.disable;
clk = clk_register(NULL, &pll_clk->hw.hw);
if (WARN_ON(IS_ERR(clk))) {
diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
index bcd3f14e9145..9faa80ff3b53 100644
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -138,8 +138,6 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
pll_clk->hw.hw.init = &init;
pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
- clk_pll_ops.enable = clk_gate_ops.enable;
- clk_pll_ops.disable = clk_gate_ops.disable;
clk = clk_register(NULL, &pll_clk->hw.hw);
if (WARN_ON(IS_ERR(clk))) {
diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c
index dc65cc0fd3bd..a001641b2f42 100644
--- a/drivers/clk/socfpga/clk-pll.c
+++ b/drivers/clk/socfpga/clk-pll.c
@@ -105,8 +105,6 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node,
pll_clk->hw.hw.init = &init;
pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
- clk_pll_ops.enable = clk_gate_ops.enable;
- clk_pll_ops.disable = clk_gate_ops.disable;
clk = clk_register(NULL, &pll_clk->hw.hw);
if (WARN_ON(IS_ERR(clk))) {
--
2.25.1
next prev parent reply other threads:[~2020-04-06 16:04 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-06 16:04 [PATCHv6 0/5] clk: agilex: add clock driver Dinh Nguyen
2020-04-06 16:04 ` [PATCHv6 1/5] clk: socfpga: stratix10: use new parent data scheme Dinh Nguyen
2020-04-06 16:04 ` Dinh Nguyen [this message]
2020-04-06 16:04 ` [PATCHv6 3/5] clk: socfpga: add const to _ops data structures Dinh Nguyen
2020-04-06 16:04 ` [PATCHv6 4/5] dt-bindings: documentation: add clock bindings information for Agilex Dinh Nguyen
2020-04-15 14:40 ` Rob Herring
2020-04-06 16:04 ` [PATCHv6 5/5] clk: socfpga: agilex: add clock driver for the Agilex platform Dinh Nguyen
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