From: Masami Hiramatsu <mhiramat@kernel.org>
To: Peter Zijlstra <peterz@infradead.org>
Cc: "Christian König" <christian.koenig@amd.com>,
"Jann Horn" <jannh@google.com>,
"Harry Wentland" <harry.wentland@amd.com>,
"Leo Li" <sunpeng.li@amd.com>,
amd-gfx@lists.freedesktop.org,
"Alex Deucher" <alexander.deucher@amd.com>,
"David Zhou" <David1.Zhou@amd.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Ingo Molnar" <mingo@redhat.com>,
"Borislav Petkov" <bp@alien8.de>,
"H . Peter Anvin" <hpa@zytor.com>,
"the arch/x86 maintainers" <x86@kernel.org>,
"kernel list" <linux-kernel@vger.kernel.org>,
"Josh Poimboeuf" <jpoimboe@redhat.com>,
"Andy Lutomirski" <luto@kernel.org>,
"Arnaldo Carvalho de Melo" <acme@kernel.org>
Subject: [PATCH] x86: insn: Add insn_is_fpu()
Date: Wed, 8 Apr 2020 00:43:48 +0900 [thread overview]
Message-ID: <158627422834.32395.5223964021388095786.stgit@devnote2> (raw)
In-Reply-To: <20200408004111.3dd597f2a7c6172b4c71a9ba@kernel.org>
Add insn_is_fpu(insn) which tells that the insn is
whether touch the MMX/XMM/YMM register or the instruction
of FP coprocessor.
Signed-off-by: Masami Hiramatsu <mhiramat@kernel.org>
---
Changes:
- Fix non-argument mmx/sse opcode pattern
- Fix to add INAT_FPUIFVEX if the first opcode isn't FPU but 2nd is FPU
instead of mnemonic pattern.
---
arch/x86/include/asm/inat.h | 7 ++++
arch/x86/include/asm/insn.h | 12 +++++++
arch/x86/lib/x86-opcode-map.txt | 25 ++++++++------
arch/x86/tools/gen-insn-attr-x86.awk | 51 ++++++++++++++++++++++++----
tools/arch/x86/include/asm/inat.h | 7 ++++
tools/arch/x86/include/asm/insn.h | 12 +++++++
tools/arch/x86/lib/x86-opcode-map.txt | 25 ++++++++------
tools/arch/x86/tools/gen-insn-attr-x86.awk | 51 ++++++++++++++++++++++++----
8 files changed, 154 insertions(+), 36 deletions(-)
diff --git a/arch/x86/include/asm/inat.h b/arch/x86/include/asm/inat.h
index 4cf2ad521f65..ffce45178c08 100644
--- a/arch/x86/include/asm/inat.h
+++ b/arch/x86/include/asm/inat.h
@@ -77,6 +77,8 @@
#define INAT_VEXOK (1 << (INAT_FLAG_OFFS + 5))
#define INAT_VEXONLY (1 << (INAT_FLAG_OFFS + 6))
#define INAT_EVEXONLY (1 << (INAT_FLAG_OFFS + 7))
+#define INAT_FPU (1 << (INAT_FLAG_OFFS + 8))
+#define INAT_FPUIFVEX (1 << (INAT_FLAG_OFFS + 9))
/* Attribute making macros for attribute tables */
#define INAT_MAKE_PREFIX(pfx) (pfx << INAT_PFX_OFFS)
#define INAT_MAKE_ESCAPE(esc) (esc << INAT_ESC_OFFS)
@@ -227,4 +229,9 @@ static inline int inat_must_evex(insn_attr_t attr)
{
return attr & INAT_EVEXONLY;
}
+
+static inline int inat_is_fpu(insn_attr_t attr)
+{
+ return attr & INAT_FPU;
+}
#endif
diff --git a/arch/x86/include/asm/insn.h b/arch/x86/include/asm/insn.h
index 5c1ae3eff9d4..1752c54d2103 100644
--- a/arch/x86/include/asm/insn.h
+++ b/arch/x86/include/asm/insn.h
@@ -129,6 +129,18 @@ static inline int insn_is_evex(struct insn *insn)
return (insn->vex_prefix.nbytes == 4);
}
+static inline int insn_is_fpu(struct insn *insn)
+{
+ if (!insn->opcode.got)
+ insn_get_opcode(insn);
+ if (inat_is_fpu(insn->attr)) {
+ if (insn->attr & INAT_FPUIFVEX)
+ return insn_is_avx(insn);
+ return 1;
+ }
+ return 0;
+}
+
static inline int insn_has_emulate_prefix(struct insn *insn)
{
return !!insn->emulate_prefix_size;
diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt
index ec31f5b60323..5470d378731a 100644
--- a/arch/x86/lib/x86-opcode-map.txt
+++ b/arch/x86/lib/x86-opcode-map.txt
@@ -269,14 +269,17 @@ d4: AAM Ib (i64)
d5: AAD Ib (i64)
d6:
d7: XLAT/XLATB
-d8: ESC
-d9: ESC
-da: ESC
-db: ESC
-dc: ESC
-dd: ESC
-de: ESC
-df: ESC
+# Intel SDM Appendix A Opcode Map shows these opcode are ESC (Escape to
+# coprocessor instruction set). Since the coprocessor means only x87 FPU
+# now, make it "x87" instead of "ESC".
+d8: x87
+d9: x87
+da: x87
+db: x87
+dc: x87
+dd: x87
+de: x87
+df: x87
# 0xe0 - 0xef
# Note: "forced64" is Intel CPU behavior: they ignore 0x66 prefix
# in 64-bit mode. AMD CPUs accept 0x66 prefix, it causes RIP truncation
@@ -1037,9 +1040,9 @@ EndTable
GrpTable: Grp15
0: fxsave | RDFSBASE Ry (F3),(11B)
-1: fxstor | RDGSBASE Ry (F3),(11B)
-2: vldmxcsr Md (v1) | WRFSBASE Ry (F3),(11B)
-3: vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B)
+1: fxrstor | RDGSBASE Ry (F3),(11B)
+2: ldmxcsr | vldmxcsr Md (v1) | WRFSBASE Ry (F3),(11B)
+3: stmxcsr | vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B)
4: XSAVE | ptwrite Ey (F3),(11B)
5: XRSTOR | lfence (11B) | INCSSPD/Q Ry (F3),(11B)
6: XSAVEOPT | clwb (66) | mfence (11B) | TPAUSE Rd (66),(11B) | UMONITOR Rv (F3),(11B) | UMWAIT Rd (F2),(11B) | CLRSSBSY Mq (F3)
diff --git a/arch/x86/tools/gen-insn-attr-x86.awk b/arch/x86/tools/gen-insn-attr-x86.awk
index a42015b305f4..d74d9e605723 100644
--- a/arch/x86/tools/gen-insn-attr-x86.awk
+++ b/arch/x86/tools/gen-insn-attr-x86.awk
@@ -65,7 +65,10 @@ BEGIN {
modrm_expr = "^([CDEGMNPQRSUVW/][a-z]+|NTA|T[012])"
force64_expr = "\\([df]64\\)"
rex_expr = "^REX(\\.[XRWB]+)*"
- fpu_expr = "^ESC" # TODO
+
+ mmxreg_expr = "^[HLNPQUVW][a-z]+" # MMX/SSE register operands
+ mmx_expr = "^(emms|fxsave|fxrstor|ldmxcsr|stmxcsr)" # MMX/SSE nmemonics lacking operands
+ fpu_expr = "^x87"
lprefix1_expr = "\\((66|!F3)\\)"
lprefix2_expr = "\\(F3\\)"
@@ -236,10 +239,11 @@ function add_flags(old,new) {
}
# convert operands to flags.
-function convert_operands(count,opnd, i,j,imm,mod)
+function convert_operands(count,opnd, i,j,imm,mod,mmx)
{
imm = null
mod = null
+ mmx = null
for (j = 1; j <= count; j++) {
i = opnd[j]
if (match(i, imm_expr) == 1) {
@@ -253,7 +257,12 @@ function convert_operands(count,opnd, i,j,imm,mod)
imm = imm_flag[i]
} else if (match(i, modrm_expr))
mod = "INAT_MODRM"
+ if (match(i, mmxreg_expr) == 1) {
+ mmx = "INAT_FPU"
+ }
}
+ if (mmx)
+ imm = add_flags(imm, mmx)
return add_flags(imm, mod)
}
@@ -283,6 +292,10 @@ function convert_operands(count,opnd, i,j,imm,mod)
variant = null
# converts
i = 2
+ lpfpu[0] = 0
+ lpfpu[1] = 0
+ lpfpu[2] = 0
+ lpfpu[3] = 0
while (i <= NF) {
opcode = $(i++)
delete opnds
@@ -294,6 +307,7 @@ function convert_operands(count,opnd, i,j,imm,mod)
opnd = $i
count = split($(i++), opnds, ",")
flags = convert_operands(count, opnds)
+
}
if (match($i, ext_expr))
ext = $(i++)
@@ -318,9 +332,9 @@ function convert_operands(count,opnd, i,j,imm,mod)
if (match(opcode, rex_expr))
flags = add_flags(flags, "INAT_MAKE_PREFIX(INAT_PFX_REX)")
- # check coprocessor escape : TODO
- if (match(opcode, fpu_expr))
- flags = add_flags(flags, "INAT_MODRM")
+ # check coprocessor escape
+ if (match(opcode, fpu_expr) || match(opcode, mmx_expr))
+ flags = add_flags(flags, "INAT_MODRM | INAT_FPU")
# check VEX codes
if (match(ext, evexonly_expr))
@@ -336,22 +350,45 @@ function convert_operands(count,opnd, i,j,imm,mod)
semantic_error("Unknown prefix: " opcode)
flags = add_flags(flags, "INAT_MAKE_PREFIX(" prefix_num[opcode] ")")
}
- if (length(flags) == 0)
- continue
+
# check if last prefix
if (match(ext, lprefix1_expr)) {
+ if (lpfpu[1] == 0 && flags !~ "INAT_FPU")
+ lpfpu[1] = 1
+ else if (lpfpu[1] != 0 && flags ~ "INAT_FPU")
+ flags = add_flags(flags, "INAT_FPUIFVEX")
+ if (length(flags) == 0)
+ continue;
lptable1[idx] = add_flags(lptable1[idx],flags)
variant = "INAT_VARIANT"
}
if (match(ext, lprefix2_expr)) {
+ if (lpfpu[2] == 0 && flags !~ "INAT_FPU")
+ lpfpu[2] = 1
+ else if (lpfpu[2] != 0 && flags ~ "INAT_FPU")
+ flags = add_flags(flags, "INAT_FPUIFVEX")
+ if (length(flags) == 0)
+ continue;
lptable2[idx] = add_flags(lptable2[idx],flags)
variant = "INAT_VARIANT"
}
if (match(ext, lprefix3_expr)) {
+ if (lpfpu[3] == 0 && flags !~ "INAT_FPU")
+ lpfpu[3] = 1
+ else if (lpfpu[3] != 0 && flags ~ "INAT_FPU")
+ flags = add_flags(flags, "INAT_FPUIFVEX")
+ if (length(flags) == 0)
+ continue;
lptable3[idx] = add_flags(lptable3[idx],flags)
variant = "INAT_VARIANT"
}
if (!match(ext, lprefix_expr)){
+ if (lpfpu[0] == 0 && flags !~ "INAT_FPU")
+ lpfpu[0] = 1
+ else if (lpfpu[0] != 0 && flags ~ "INAT_FPU")
+ flags = add_flags(flags, "INAT_FPUIFVEX")
+ if (length(flags) == 0)
+ continue;
table[idx] = add_flags(table[idx],flags)
}
}
diff --git a/tools/arch/x86/include/asm/inat.h b/tools/arch/x86/include/asm/inat.h
index 877827b7c2c3..2e6a05290efd 100644
--- a/tools/arch/x86/include/asm/inat.h
+++ b/tools/arch/x86/include/asm/inat.h
@@ -77,6 +77,8 @@
#define INAT_VEXOK (1 << (INAT_FLAG_OFFS + 5))
#define INAT_VEXONLY (1 << (INAT_FLAG_OFFS + 6))
#define INAT_EVEXONLY (1 << (INAT_FLAG_OFFS + 7))
+#define INAT_FPU (1 << (INAT_FLAG_OFFS + 8))
+#define INAT_FPUIFVEX (1 << (INAT_FLAG_OFFS + 9))
/* Attribute making macros for attribute tables */
#define INAT_MAKE_PREFIX(pfx) (pfx << INAT_PFX_OFFS)
#define INAT_MAKE_ESCAPE(esc) (esc << INAT_ESC_OFFS)
@@ -227,4 +229,9 @@ static inline int inat_must_evex(insn_attr_t attr)
{
return attr & INAT_EVEXONLY;
}
+
+static inline int inat_is_fpu(insn_attr_t attr)
+{
+ return attr & INAT_FPU;
+}
#endif
diff --git a/tools/arch/x86/include/asm/insn.h b/tools/arch/x86/include/asm/insn.h
index 568854b14d0a..d9f6bd9059c1 100644
--- a/tools/arch/x86/include/asm/insn.h
+++ b/tools/arch/x86/include/asm/insn.h
@@ -129,6 +129,18 @@ static inline int insn_is_evex(struct insn *insn)
return (insn->vex_prefix.nbytes == 4);
}
+static inline int insn_is_fpu(struct insn *insn)
+{
+ if (!insn->opcode.got)
+ insn_get_opcode(insn);
+ if (inat_is_fpu(insn->attr)) {
+ if (insn->attr & INAT_FPUIFVEX)
+ return insn_is_avx(insn);
+ return 1;
+ }
+ return 0;
+}
+
static inline int insn_has_emulate_prefix(struct insn *insn)
{
return !!insn->emulate_prefix_size;
diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86-opcode-map.txt
index ec31f5b60323..5470d378731a 100644
--- a/tools/arch/x86/lib/x86-opcode-map.txt
+++ b/tools/arch/x86/lib/x86-opcode-map.txt
@@ -269,14 +269,17 @@ d4: AAM Ib (i64)
d5: AAD Ib (i64)
d6:
d7: XLAT/XLATB
-d8: ESC
-d9: ESC
-da: ESC
-db: ESC
-dc: ESC
-dd: ESC
-de: ESC
-df: ESC
+# Intel SDM Appendix A Opcode Map shows these opcode are ESC (Escape to
+# coprocessor instruction set). Since the coprocessor means only x87 FPU
+# now, make it "x87" instead of "ESC".
+d8: x87
+d9: x87
+da: x87
+db: x87
+dc: x87
+dd: x87
+de: x87
+df: x87
# 0xe0 - 0xef
# Note: "forced64" is Intel CPU behavior: they ignore 0x66 prefix
# in 64-bit mode. AMD CPUs accept 0x66 prefix, it causes RIP truncation
@@ -1037,9 +1040,9 @@ EndTable
GrpTable: Grp15
0: fxsave | RDFSBASE Ry (F3),(11B)
-1: fxstor | RDGSBASE Ry (F3),(11B)
-2: vldmxcsr Md (v1) | WRFSBASE Ry (F3),(11B)
-3: vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B)
+1: fxrstor | RDGSBASE Ry (F3),(11B)
+2: ldmxcsr | vldmxcsr Md (v1) | WRFSBASE Ry (F3),(11B)
+3: stmxcsr | vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B)
4: XSAVE | ptwrite Ey (F3),(11B)
5: XRSTOR | lfence (11B) | INCSSPD/Q Ry (F3),(11B)
6: XSAVEOPT | clwb (66) | mfence (11B) | TPAUSE Rd (66),(11B) | UMONITOR Rv (F3),(11B) | UMWAIT Rd (F2),(11B) | CLRSSBSY Mq (F3)
diff --git a/tools/arch/x86/tools/gen-insn-attr-x86.awk b/tools/arch/x86/tools/gen-insn-attr-x86.awk
index a42015b305f4..d74d9e605723 100644
--- a/tools/arch/x86/tools/gen-insn-attr-x86.awk
+++ b/tools/arch/x86/tools/gen-insn-attr-x86.awk
@@ -65,7 +65,10 @@ BEGIN {
modrm_expr = "^([CDEGMNPQRSUVW/][a-z]+|NTA|T[012])"
force64_expr = "\\([df]64\\)"
rex_expr = "^REX(\\.[XRWB]+)*"
- fpu_expr = "^ESC" # TODO
+
+ mmxreg_expr = "^[HLNPQUVW][a-z]+" # MMX/SSE register operands
+ mmx_expr = "^(emms|fxsave|fxrstor|ldmxcsr|stmxcsr)" # MMX/SSE nmemonics lacking operands
+ fpu_expr = "^x87"
lprefix1_expr = "\\((66|!F3)\\)"
lprefix2_expr = "\\(F3\\)"
@@ -236,10 +239,11 @@ function add_flags(old,new) {
}
# convert operands to flags.
-function convert_operands(count,opnd, i,j,imm,mod)
+function convert_operands(count,opnd, i,j,imm,mod,mmx)
{
imm = null
mod = null
+ mmx = null
for (j = 1; j <= count; j++) {
i = opnd[j]
if (match(i, imm_expr) == 1) {
@@ -253,7 +257,12 @@ function convert_operands(count,opnd, i,j,imm,mod)
imm = imm_flag[i]
} else if (match(i, modrm_expr))
mod = "INAT_MODRM"
+ if (match(i, mmxreg_expr) == 1) {
+ mmx = "INAT_FPU"
+ }
}
+ if (mmx)
+ imm = add_flags(imm, mmx)
return add_flags(imm, mod)
}
@@ -283,6 +292,10 @@ function convert_operands(count,opnd, i,j,imm,mod)
variant = null
# converts
i = 2
+ lpfpu[0] = 0
+ lpfpu[1] = 0
+ lpfpu[2] = 0
+ lpfpu[3] = 0
while (i <= NF) {
opcode = $(i++)
delete opnds
@@ -294,6 +307,7 @@ function convert_operands(count,opnd, i,j,imm,mod)
opnd = $i
count = split($(i++), opnds, ",")
flags = convert_operands(count, opnds)
+
}
if (match($i, ext_expr))
ext = $(i++)
@@ -318,9 +332,9 @@ function convert_operands(count,opnd, i,j,imm,mod)
if (match(opcode, rex_expr))
flags = add_flags(flags, "INAT_MAKE_PREFIX(INAT_PFX_REX)")
- # check coprocessor escape : TODO
- if (match(opcode, fpu_expr))
- flags = add_flags(flags, "INAT_MODRM")
+ # check coprocessor escape
+ if (match(opcode, fpu_expr) || match(opcode, mmx_expr))
+ flags = add_flags(flags, "INAT_MODRM | INAT_FPU")
# check VEX codes
if (match(ext, evexonly_expr))
@@ -336,22 +350,45 @@ function convert_operands(count,opnd, i,j,imm,mod)
semantic_error("Unknown prefix: " opcode)
flags = add_flags(flags, "INAT_MAKE_PREFIX(" prefix_num[opcode] ")")
}
- if (length(flags) == 0)
- continue
+
# check if last prefix
if (match(ext, lprefix1_expr)) {
+ if (lpfpu[1] == 0 && flags !~ "INAT_FPU")
+ lpfpu[1] = 1
+ else if (lpfpu[1] != 0 && flags ~ "INAT_FPU")
+ flags = add_flags(flags, "INAT_FPUIFVEX")
+ if (length(flags) == 0)
+ continue;
lptable1[idx] = add_flags(lptable1[idx],flags)
variant = "INAT_VARIANT"
}
if (match(ext, lprefix2_expr)) {
+ if (lpfpu[2] == 0 && flags !~ "INAT_FPU")
+ lpfpu[2] = 1
+ else if (lpfpu[2] != 0 && flags ~ "INAT_FPU")
+ flags = add_flags(flags, "INAT_FPUIFVEX")
+ if (length(flags) == 0)
+ continue;
lptable2[idx] = add_flags(lptable2[idx],flags)
variant = "INAT_VARIANT"
}
if (match(ext, lprefix3_expr)) {
+ if (lpfpu[3] == 0 && flags !~ "INAT_FPU")
+ lpfpu[3] = 1
+ else if (lpfpu[3] != 0 && flags ~ "INAT_FPU")
+ flags = add_flags(flags, "INAT_FPUIFVEX")
+ if (length(flags) == 0)
+ continue;
lptable3[idx] = add_flags(lptable3[idx],flags)
variant = "INAT_VARIANT"
}
if (!match(ext, lprefix_expr)){
+ if (lpfpu[0] == 0 && flags !~ "INAT_FPU")
+ lpfpu[0] = 1
+ else if (lpfpu[0] != 0 && flags ~ "INAT_FPU")
+ flags = add_flags(flags, "INAT_FPUIFVEX")
+ if (length(flags) == 0)
+ continue;
table[idx] = add_flags(table[idx],flags)
}
}
next prev parent reply other threads:[~2020-04-07 15:43 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-02 2:34 AMD DC graphics display code enables -mhard-float, -msse, -msse2 without any visible FPU state protection Jann Horn
2020-04-02 7:33 ` Christian König
2020-04-02 7:56 ` Jann Horn
2020-04-02 9:36 ` Thomas Gleixner
2020-04-02 14:50 ` Jann Horn
2020-04-02 14:13 ` Peter Zijlstra
2020-04-03 5:28 ` Masami Hiramatsu
2020-04-03 11:21 ` Peter Zijlstra
2020-04-04 3:08 ` Masami Hiramatsu
2020-04-04 3:15 ` Randy Dunlap
2020-04-04 8:32 ` Masami Hiramatsu
2020-04-04 14:32 ` Peter Zijlstra
2020-04-05 3:19 ` Masami Hiramatsu
2020-04-06 10:21 ` Peter Zijlstra
2020-04-07 9:50 ` Masami Hiramatsu
2020-04-07 11:15 ` Peter Zijlstra
2020-04-07 15:41 ` Masami Hiramatsu
2020-04-07 15:43 ` Masami Hiramatsu [this message]
2020-04-07 15:54 ` Peter Zijlstra
2020-04-08 0:31 ` Masami Hiramatsu
2020-04-08 16:09 ` [PATCH v2] x86: insn: Add insn_is_fpu() Masami Hiramatsu
2020-04-09 14:32 ` Peter Zijlstra
2020-04-09 14:45 ` Peter Zijlstra
2020-04-10 0:47 ` Masami Hiramatsu
2020-04-10 1:22 ` [PATCH v3] " Masami Hiramatsu
2020-04-15 8:23 ` Masami Hiramatsu
2020-04-15 8:49 ` [PATCH v4] " Masami Hiramatsu
2020-04-04 14:36 ` AMD DC graphics display code enables -mhard-float, -msse, -msse2 without any visible FPU state protection Peter Zijlstra
2020-04-05 3:37 ` Masami Hiramatsu
2020-04-09 15:59 ` Peter Zijlstra
2020-04-09 17:09 ` Peter Zijlstra
2020-04-09 18:15 ` Christian König
2020-04-09 20:01 ` Peter Zijlstra
2020-04-10 14:31 ` Christian König
2020-04-15 9:16 ` Peter Zijlstra
2020-04-17 20:27 ` Rodrigo Siqueira
2020-04-17 21:56 ` Peter Zijlstra
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