From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Rob Herring <robh+dt@kernel.org>,
Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Subject: [PATCH 1/3] dt-bindings: phy: Convert UniPhier PCIe-PHY controller to json-schema
Date: Tue, 28 Apr 2020 15:34:48 +0900 [thread overview]
Message-ID: <1588055690-13200-1-git-send-email-hayashi.kunihiko@socionext.com> (raw)
Convert the UniPhier PCIe-PHY controller to DT schema format.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
.../bindings/phy/socionext,uniphier-pcie-phy.yaml | 77 ++++++++++++++++++++++
.../devicetree/bindings/phy/uniphier-pcie-phy.txt | 36 ----------
2 files changed, 77 insertions(+), 36 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml
new file mode 100644
index 0000000..86f4909
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier PCIe PHY
+
+description: |
+ This describes the devicetree bindings for PHY interface built into
+ PCIe controller implemented on Socionext UniPhier SoCs.
+
+maintainers:
+ - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+properties:
+ compatible:
+ enum:
+ - socionext,uniphier-pro5-pcie-phy
+ - socionext,uniphier-ld20-pcie-phy
+ - socionext,uniphier-pxs3-pcie-phy
+
+ reg:
+ description: PHY register region (offset and length)
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ oneOf:
+ - items: # for Pro5
+ - const: gio
+ - const: link
+ - const: link # for others
+
+ resets:
+ minItems: 1
+ maxItems: 2
+
+ reset-names:
+ oneOf:
+ - items: # for Pro5
+ - const: gio
+ - const: link
+ - const: link # for others
+
+ socionext,syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: A phandle to system control to set configurations for phy
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ pcie_phy: phy@66038000 {
+ compatible = "socionext,uniphier-ld20-pcie-phy";
+ reg = <0x66038000 0x4000>;
+ #phy-cells = <0>;
+ clock-names = "link";
+ clocks = <&sys_clk 24>;
+ reset-names = "link";
+ resets = <&sys_rst 24>;
+ socionext,syscon = <&soc_glue>;
+ };
diff --git a/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt b/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt
deleted file mode 100644
index 3cee372..0000000
--- a/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Socionext UniPhier PCIe PHY bindings
-
-This describes the devicetree bindings for PHY interface built into
-PCIe controller implemented on Socionext UniPhier SoCs.
-
-Required properties:
-- compatible: Should contain one of the following:
- "socionext,uniphier-pro5-pcie-phy" - for Pro5 PHY
- "socionext,uniphier-ld20-pcie-phy" - for LD20 PHY
- "socionext,uniphier-pxs3-pcie-phy" - for PXs3 PHY
-- reg: Specifies offset and length of the register set for the device.
-- #phy-cells: Must be zero.
-- clocks: A list of phandles to the clock gate for PCIe glue layer
- including this phy.
-- clock-names: For Pro5 only, should contain the following:
- "gio", "link" - for Pro5 SoC
-- resets: A list of phandles to the reset line for PCIe glue layer
- including this phy.
-- reset-names: For Pro5 only, should contain the following:
- "gio", "link" - for Pro5 SoC
-
-Optional properties:
-- socionext,syscon: A phandle to system control to set configurations
- for phy.
-
-Refer to phy/phy-bindings.txt for the generic PHY binding properties.
-
-Example:
- pcie_phy: phy@66038000 {
- compatible = "socionext,uniphier-ld20-pcie-phy";
- reg = <0x66038000 0x4000>;
- #phy-cells = <0>;
- clocks = <&sys_clk 24>;
- resets = <&sys_rst 24>;
- socionext,syscon = <&soc_glue>;
- };
--
2.7.4
next reply other threads:[~2020-04-28 6:35 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-28 6:34 Kunihiko Hayashi [this message]
2020-04-28 6:34 ` [PATCH 2/3] dt-bindings: phy: Convert UniPhier USB2-PHY controller to json-schema Kunihiko Hayashi
2020-05-12 2:04 ` Rob Herring
2020-04-28 6:34 ` [PATCH 3/3] dt-bindings: phy: Convert UniPhier USB3-PHY conroller " Kunihiko Hayashi
2020-05-12 2:04 ` Rob Herring
2020-05-12 2:03 ` [PATCH 1/3] dt-bindings: phy: Convert UniPhier PCIe-PHY controller " Rob Herring
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