From: Sarthak Garg <sartgarg@codeaurora.org>
To: adrian.hunter@intel.com, ulf.hansson@linaro.org
Cc: vbadigan@codeaurora.org, stummala@codeaurora.org,
linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-msm@vger.kernel.org,
Sarthak Garg <sartgarg@codeaurora.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>
Subject: [PATCH V2 4/8] mmc: sdhci-msm: Update dll_config_3 as per HSR
Date: Fri, 22 May 2020 15:02:26 +0530 [thread overview]
Message-ID: <1590139950-7288-5-git-send-email-sartgarg@codeaurora.org> (raw)
In-Reply-To: <1590139950-7288-1-git-send-email-sartgarg@codeaurora.org>
Update dll_config_3 as per the host clock frequency as specified in the
DLL Hardware Reference Guide.
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci-msm.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 6588077..054b151 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -62,6 +62,9 @@
#define FINE_TUNE_MODE_EN BIT(27)
#define BIAS_OK_SIGNAL BIT(29)
+#define DLL_CONFIG_3_LOW_FREQ_VAL 0x08
+#define DLL_CONFIG_3_HIGH_FREQ_VAL 0x10
+
#define CORE_VENDOR_SPEC_POR_VAL 0xa9c
#define CORE_CLK_PWRSAVE BIT(1)
#define CORE_HC_MCLK_SEL_DFLT (2 << 8)
@@ -695,6 +698,16 @@ static int msm_init_cm_dll(struct sdhci_host *host)
ENABLE_DLL_LOCK_STATUS | BIAS_OK_SIGNAL;
writel_relaxed(config, host->ioaddr +
msm_offset->core_dll_usr_ctl);
+
+ config = readl_relaxed(host->ioaddr +
+ msm_offset->core_dll_config_3);
+ config &= ~0xFF;
+ if (msm_host->clk_rate < 150000000)
+ config |= DLL_CONFIG_3_LOW_FREQ_VAL;
+ else
+ config |= DLL_CONFIG_3_HIGH_FREQ_VAL;
+ writel_relaxed(config, host->ioaddr +
+ msm_offset->core_dll_config_3);
}
config = readl_relaxed(host->ioaddr +
--
2.7.4
next prev parent reply other threads:[~2020-05-22 9:37 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-07 8:02 [PATCH V1 0/7] Target specific DLL configuration for qcom SDHC Sarthak Garg
2020-05-07 8:02 ` [PATCH V1 1/7] dt-bindings: mmc: Add information for DLL register properties Sarthak Garg
2020-05-15 2:50 ` Rob Herring
2020-05-19 14:00 ` sartgarg
2020-05-20 11:33 ` Ulf Hansson
2020-05-07 8:02 ` [PATCH V1 2/7] mmc: host: sdhci-msm: Configure dll-user-control in dll init sequence Sarthak Garg
2020-05-07 8:02 ` [PATCH V1 3/7] mmc: sdhci-msm: Update dll_config_3 as per HSR Sarthak Garg
2020-05-07 8:02 ` [PATCH V1 4/7] mmc: sdhci-msm: Update DDR_CONFIG as per device tree file Sarthak Garg
2020-05-07 8:02 ` [PATCH V1 5/7] mmc: sdhci-msm: Read and use DLL Config property from " Sarthak Garg
2020-05-07 8:02 ` [PATCH V1 6/7] mmc: sdhci-msm: Introduce new ops to dump vendor specific registers Sarthak Garg
2020-05-07 8:02 ` [PATCH V1 7/7] mmc: sdhci-msm: dump vendor specific registers during error Sarthak Garg
2020-05-15 14:32 ` [PATCH V1 0/7] Target specific DLL configuration for qcom SDHC Adrian Hunter
2020-05-22 9:23 ` [PATCH V2 0/8] Board " Sarthak Garg
2020-05-22 9:32 ` Sarthak Garg
2020-05-22 9:32 ` [PATCH V2 1/8] dt-bindings: mmc: Add new compatible string for sm8250 target Sarthak Garg
2020-05-22 9:32 ` [PATCH V2 2/8] dt-bindings: mmc: Add information for DLL register properties Sarthak Garg
2020-05-22 9:32 ` [PATCH V2 3/8] mmc: host: sdhci-msm: Configure dll-user-control in dll init sequence Sarthak Garg
2020-05-22 9:32 ` Sarthak Garg [this message]
2020-05-22 9:32 ` [PATCH V2 5/8] mmc: sdhci-msm: Update DDR_CONFIG as per device tree file Sarthak Garg
2020-05-22 9:32 ` [PATCH V2 6/8] mmc: sdhci-msm: Read and use DLL Config property from " Sarthak Garg
2020-05-22 9:32 ` [PATCH V2 7/8] mmc: sdhci-msm: Introduce new ops to dump vendor specific registers Sarthak Garg
2020-05-22 9:32 ` [PATCH V2 8/8] mmc: sdhci-msm: dump vendor specific registers during error Sarthak Garg
2020-05-25 8:47 ` [PATCH V2 0/8] Board specific DLL configuration for qcom SDHC Ulf Hansson
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