From: Greentime Hu <greentime.hu@sifive.com>
To: greentime.hu@sifive.com, guoren@linux.alibaba.com,
vincent.chen@sifive.com, paul.walmsley@sifive.com,
palmerdabbelt@google.com, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, oleg@redhat.com
Subject: [RFC PATCH v4 08/13] riscv: Reset vector register
Date: Tue, 26 May 2020 15:02:37 +0800 [thread overview]
Message-ID: <2424daf7c5b704b5c4ea2c317304d7fd0cf7ef2a.1590474856.git.greentime.hu@sifive.com> (raw)
In-Reply-To: <cover.1590474856.git.greentime.hu@sifive.com>
From: Guo Ren <guoren@linux.alibaba.com>
Reset vector registers at boot-time and disable vector instructions
execution for kernel mode.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
---
arch/riscv/kernel/entry.S | 2 +-
arch/riscv/kernel/head.S | 49 +++++++++++++++++++++++++++++++++++++--
2 files changed, 48 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 56d071b2c0a1..4e32770c19c8 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -70,7 +70,7 @@ _save_context:
* Disable the FPU to detect illegal usage of floating point in kernel
* space.
*/
- li t0, SR_SUM | SR_FS
+ li t0, SR_SUM | SR_FS | SR_VS
REG_L s0, TASK_TI_USER_SP(tp)
csrrc s1, CSR_STATUS, t0
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 98a406474e7d..1290ef680125 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -181,10 +181,10 @@ ENTRY(_start_kernel)
.option pop
/*
- * Disable FPU to detect illegal usage of
+ * Disable FPU & VECTOR to detect illegal usage of
* floating point in kernel space
*/
- li t0, SR_FS
+ li t0, SR_FS | SR_VS
csrc CSR_STATUS, t0
#ifdef CONFIG_SMP
@@ -341,6 +341,51 @@ ENTRY(reset_regs)
csrw fcsr, 0
/* note that the caller must clear SR_FS */
#endif /* CONFIG_FPU */
+
+#ifdef CONFIG_VECTOR
+ csrr t0, CSR_MISA
+ li t1, (COMPAT_HWCAP_ISA_V >> 16)
+ slli t1, t1, 16
+ and t0, t0, t1
+ beqz t0, .Lreset_regs_done
+
+ li t1, SR_VS
+ csrs CSR_STATUS, t1
+ vmv.v.i v0, 0
+ vmv.v.i v1, 0
+ vmv.v.i v2, 0
+ vmv.v.i v3, 0
+ vmv.v.i v4, 0
+ vmv.v.i v5, 0
+ vmv.v.i v6, 0
+ vmv.v.i v7, 0
+ vmv.v.i v8, 0
+ vmv.v.i v9, 0
+ vmv.v.i v10, 0
+ vmv.v.i v11, 0
+ vmv.v.i v12, 0
+ vmv.v.i v13, 0
+ vmv.v.i v14, 0
+ vmv.v.i v15, 0
+ vmv.v.i v16, 0
+ vmv.v.i v17, 0
+ vmv.v.i v18, 0
+ vmv.v.i v19, 0
+ vmv.v.i v20, 0
+ vmv.v.i v21, 0
+ vmv.v.i v22, 0
+ vmv.v.i v23, 0
+ vmv.v.i v24, 0
+ vmv.v.i v25, 0
+ vmv.v.i v26, 0
+ vmv.v.i v27, 0
+ vmv.v.i v28, 0
+ vmv.v.i v29, 0
+ vmv.v.i v30, 0
+ vmv.v.i v31, 0
+ /* note that the caller must clear SR_VS */
+#endif /* CONFIG_VECTOR */
+
.Lreset_regs_done:
ret
END(reset_regs)
--
2.26.2
next prev parent reply other threads:[~2020-05-26 7:03 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-26 7:02 [RFC PATCH v4 00/13] riscv: Add vector ISA support Greentime Hu
2020-05-26 7:02 ` [RFC PATCH v4 01/13] ptrace: Use regset_size() for dynamic regset size Greentime Hu
2020-05-26 14:00 ` Oleg Nesterov
2020-05-27 6:34 ` Greentime Hu
2020-05-27 11:31 ` Oleg Nesterov
2020-05-26 7:02 ` [RFC PATCH v4 02/13] riscv: Separate patch for cflags and aflags Greentime Hu
2020-05-26 7:02 ` [RFC PATCH v4 03/13] riscv: Rename __switch_to_aux -> fpu Greentime Hu
2020-05-26 7:02 ` [RFC PATCH v4 04/13] riscv: Extending cpufeature.c to detect V-extension Greentime Hu
2020-05-26 7:02 ` [RFC PATCH v4 05/13] riscv: Add new csr defines related to vector extension Greentime Hu
2020-05-31 1:56 ` Guo Ren
2020-06-01 8:15 ` Greentime Hu
2020-06-01 8:59 ` Guo Ren
2020-06-01 9:03 ` Guo Ren
2020-05-26 7:02 ` [RFC PATCH v4 06/13] riscv: Add vector feature to compile Greentime Hu
2020-05-26 7:02 ` [RFC PATCH v4 07/13] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu
2020-05-31 0:58 ` Guo Ren
2020-06-01 8:07 ` Greentime Hu
2020-06-01 9:13 ` Guo Ren
2020-05-26 7:02 ` Greentime Hu [this message]
2020-05-26 7:02 ` [RFC PATCH v4 09/13] riscv: Add vector struct and assembler definitions Greentime Hu
2020-06-01 9:12 ` Guo Ren
2020-05-26 7:02 ` [RFC PATCH v4 10/13] riscv: Add task switch support for vector Greentime Hu
2020-05-31 15:29 ` Guo Ren
2020-05-31 16:08 ` Guo Ren
2020-06-01 9:12 ` Guo Ren
2020-05-26 7:02 ` [RFC PATCH v4 11/13] riscv: Add ptrace vector support Greentime Hu
2020-06-01 9:14 ` Guo Ren
2020-05-26 7:02 ` [RFC PATCH v4 12/13] riscv: Add sigcontext save/restore for vector Greentime Hu
2020-05-31 15:28 ` Guo Ren
2020-06-01 9:13 ` Guo Ren
2020-05-26 7:02 ` [RFC PATCH v4 13/13] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu
2020-05-31 15:52 ` [RFC PATCH v4 00/13] riscv: Add vector ISA support Guo Ren
2020-06-02 2:21 ` Greentime Hu
2020-06-02 3:08 ` Guo Ren
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