From: Greentime Hu <greentime.hu@sifive.com>
To: greentime.hu@sifive.com, guoren@linux.alibaba.com,
vincent.chen@sifive.com, paul.walmsley@sifive.com,
palmerdabbelt@google.com, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, oleg@redhat.com
Cc: Anup Patel <anup@brainfault.org>
Subject: [RFC PATCH v5 03/13] riscv: Rename __switch_to_aux -> fpu
Date: Thu, 28 May 2020 14:40:51 +0800 [thread overview]
Message-ID: <690bd2391cf1a44e23d1e6e4df58c1083a71c7af.1590646208.git.greentime.hu@sifive.com> (raw)
In-Reply-To: <cover.1590646208.git.greentime.hu@sifive.com>
From: Guo Ren <guoren@linux.alibaba.com>
From: Guo Ren <ren_guo@c-sky.com>
The name of __switch_to_aux is not clear and rename it with the
determine function: __switch_to_fpu. Next we could add other regs'
switch.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
arch/riscv/include/asm/switch_to.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
index 407bcc96a710..b9234e7178d0 100644
--- a/arch/riscv/include/asm/switch_to.h
+++ b/arch/riscv/include/asm/switch_to.h
@@ -44,7 +44,7 @@ static inline void fstate_restore(struct task_struct *task,
}
}
-static inline void __switch_to_aux(struct task_struct *prev,
+static inline void __switch_to_fpu(struct task_struct *prev,
struct task_struct *next)
{
struct pt_regs *regs;
@@ -60,7 +60,7 @@ extern bool has_fpu;
#define has_fpu false
#define fstate_save(task, regs) do { } while (0)
#define fstate_restore(task, regs) do { } while (0)
-#define __switch_to_aux(__prev, __next) do { } while (0)
+#define __switch_to_fpu(__prev, __next) do { } while (0)
#endif
extern struct task_struct *__switch_to(struct task_struct *,
@@ -71,7 +71,7 @@ do { \
struct task_struct *__prev = (prev); \
struct task_struct *__next = (next); \
if (has_fpu) \
- __switch_to_aux(__prev, __next); \
+ __switch_to_fpu(__prev, __next); \
((last) = __switch_to(__prev, __next)); \
} while (0)
--
2.26.2
next prev parent reply other threads:[~2020-05-28 6:41 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-28 6:40 [RFC PATCH v5 00/13] riscv: Add vector ISA support Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 01/13] ptrace: Use regset_size() for dynamic regset Greentime Hu
2020-05-28 12:36 ` Oleg Nesterov
2020-05-28 6:40 ` [RFC PATCH v5 02/13] riscv: Separate patch for cflags and aflags Greentime Hu
2020-05-28 6:40 ` Greentime Hu [this message]
2020-05-28 6:40 ` [RFC PATCH v5 04/13] riscv: Extending cpufeature.c to detect V-extension Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 05/13] riscv: Add new csr defines related to vector extension Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 06/13] riscv: Add vector feature to compile Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 07/13] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 08/13] riscv: Reset vector register Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 09/13] riscv: Add vector struct and assembler definitions Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 10/13] riscv: Add task switch support for vector Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 11/13] riscv: Add ptrace vector support Greentime Hu
2020-05-28 6:41 ` [RFC PATCH v5 12/13] riscv: Add sigcontext save/restore for vector Greentime Hu
2020-05-28 6:41 ` [RFC PATCH v5 13/13] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu
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