From: Greentime Hu <greentime.hu@sifive.com>
To: greentime.hu@sifive.com, guoren@linux.alibaba.com,
vincent.chen@sifive.com, paul.walmsley@sifive.com,
palmerdabbelt@google.com, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, oleg@redhat.com
Subject: [RFC PATCH v5 05/13] riscv: Add new csr defines related to vector extension
Date: Thu, 28 May 2020 14:40:53 +0800 [thread overview]
Message-ID: <d17991701f346749eda2ad3d295ac5788ac89af7.1590646208.git.greentime.hu@sifive.com> (raw)
In-Reply-To: <cover.1590646208.git.greentime.hu@sifive.com>
From: Guo Ren <guoren@linux.alibaba.com>
Follow the riscv vector spec to add new csr number.
[greentime.hu@sifive.com: update the defined value based on new spec and
remove unused ones]
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
---
arch/riscv/include/asm/csr.h | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 8e18d2c64399..cc13626c4bbe 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -24,6 +24,12 @@
#define SR_FS_CLEAN _AC(0x00004000, UL)
#define SR_FS_DIRTY _AC(0x00006000, UL)
+#define SR_VS _AC(0x00000600, UL) /* Vector Status */
+#define SR_VS_OFF _AC(0x00000000, UL)
+#define SR_VS_INITIAL _AC(0x00000200, UL)
+#define SR_VS_CLEAN _AC(0x00000400, UL)
+#define SR_VS_DIRTY _AC(0x00000600, UL)
+
#define SR_XS _AC(0x00018000, UL) /* Extension Status */
#define SR_XS_OFF _AC(0x00000000, UL)
#define SR_XS_INITIAL _AC(0x00008000, UL)
@@ -31,9 +37,9 @@
#define SR_XS_DIRTY _AC(0x00018000, UL)
#ifndef CONFIG_64BIT
-#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */
+#define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */
#else
-#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */
+#define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */
#endif
/* SATP flags */
@@ -114,6 +120,12 @@
#define CSR_PMPADDR0 0x3b0
#define CSR_MHARTID 0xf14
+#define CSR_VSTART 0x8
+#define CSR_VCSR 0xf
+#define CSR_VL 0xc20
+#define CSR_VTYPE 0xc21
+#define CSR_VLENB 0xc22
+
#ifdef CONFIG_RISCV_M_MODE
# define CSR_STATUS CSR_MSTATUS
# define CSR_IE CSR_MIE
--
2.26.2
next prev parent reply other threads:[~2020-05-28 6:41 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-28 6:40 [RFC PATCH v5 00/13] riscv: Add vector ISA support Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 01/13] ptrace: Use regset_size() for dynamic regset Greentime Hu
2020-05-28 12:36 ` Oleg Nesterov
2020-05-28 6:40 ` [RFC PATCH v5 02/13] riscv: Separate patch for cflags and aflags Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 03/13] riscv: Rename __switch_to_aux -> fpu Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 04/13] riscv: Extending cpufeature.c to detect V-extension Greentime Hu
2020-05-28 6:40 ` Greentime Hu [this message]
2020-05-28 6:40 ` [RFC PATCH v5 06/13] riscv: Add vector feature to compile Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 07/13] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 08/13] riscv: Reset vector register Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 09/13] riscv: Add vector struct and assembler definitions Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 10/13] riscv: Add task switch support for vector Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 11/13] riscv: Add ptrace vector support Greentime Hu
2020-05-28 6:41 ` [RFC PATCH v5 12/13] riscv: Add sigcontext save/restore for vector Greentime Hu
2020-05-28 6:41 ` [RFC PATCH v5 13/13] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu
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