From: Greentime Hu <greentime.hu@sifive.com>
To: greentime.hu@sifive.com, guoren@linux.alibaba.com,
vincent.chen@sifive.com, paul.walmsley@sifive.com,
palmerdabbelt@google.com, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, oleg@redhat.com
Cc: Anup Patel <anup@brainfault.org>
Subject: [RFC PATCH v5 04/13] riscv: Extending cpufeature.c to detect V-extension
Date: Thu, 28 May 2020 14:40:52 +0800 [thread overview]
Message-ID: <4b2a5ec77dd0eee02818abb036518930fed8b105.1590646208.git.greentime.hu@sifive.com> (raw)
In-Reply-To: <cover.1590646208.git.greentime.hu@sifive.com>
From: Guo Ren <guoren@linux.alibaba.com>
From: Guo Ren <ren_guo@c-sky.com>
Current cpufeature.c doesn't support detecting V-extension, because
"rv64" also contain a 'v' letter and we need to skip it.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
arch/riscv/include/uapi/asm/hwcap.h | 1 +
arch/riscv/kernel/cpufeature.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h
index dee98ee28318..a913e9a38819 100644
--- a/arch/riscv/include/uapi/asm/hwcap.h
+++ b/arch/riscv/include/uapi/asm/hwcap.h
@@ -21,5 +21,6 @@
#define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A'))
#define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A'))
#define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A'))
+#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A'))
#endif /* _UAPI_ASM_RISCV_HWCAP_H */
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index a5ad00043104..c8527d770c98 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -30,6 +30,7 @@ void riscv_fill_hwcap(void)
isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F;
isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D;
isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
+ isa2hwcap['v'] = isa2hwcap['V'] = COMPAT_HWCAP_ISA_V;
elf_hwcap = 0;
@@ -44,7 +45,8 @@ void riscv_fill_hwcap(void)
continue;
}
- for (i = 0; i < strlen(isa); ++i)
+ /* Skip rv64/rv32 to support v/V:vector */
+ for (i = 4; i < strlen(isa); ++i)
this_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
/*
--
2.26.2
next prev parent reply other threads:[~2020-05-28 6:41 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-28 6:40 [RFC PATCH v5 00/13] riscv: Add vector ISA support Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 01/13] ptrace: Use regset_size() for dynamic regset Greentime Hu
2020-05-28 12:36 ` Oleg Nesterov
2020-05-28 6:40 ` [RFC PATCH v5 02/13] riscv: Separate patch for cflags and aflags Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 03/13] riscv: Rename __switch_to_aux -> fpu Greentime Hu
2020-05-28 6:40 ` Greentime Hu [this message]
2020-05-28 6:40 ` [RFC PATCH v5 05/13] riscv: Add new csr defines related to vector extension Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 06/13] riscv: Add vector feature to compile Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 07/13] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 08/13] riscv: Reset vector register Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 09/13] riscv: Add vector struct and assembler definitions Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 10/13] riscv: Add task switch support for vector Greentime Hu
2020-05-28 6:40 ` [RFC PATCH v5 11/13] riscv: Add ptrace vector support Greentime Hu
2020-05-28 6:41 ` [RFC PATCH v5 12/13] riscv: Add sigcontext save/restore for vector Greentime Hu
2020-05-28 6:41 ` [RFC PATCH v5 13/13] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu
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