From: Jim Quinlan <james.quinlan@broadcom.com>
To: linux-pci@vger.kernel.org, Christoph Hellwig <hch@lst.de>,
Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
bcm-kernel-feedback-list@broadcom.com,
james.quinlan@broadcom.com
Cc: Jim Quinlan <james.quinlan@broadcom.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Florian Fainelli <f.fainelli@gmail.com>,
linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM
BCM2711/BCM2835 ARM ARCHITECTURE),
linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM
BCM2711/BCM2835 ARM ARCHITECTURE),
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v3 12/13] PCI: brcmstb: Set bus max burst size by chip type
Date: Wed, 3 Jun 2020 15:20:44 -0400 [thread overview]
Message-ID: <20200603192058.35296-13-james.quinlan@broadcom.com> (raw)
In-Reply-To: <20200603192058.35296-1-james.quinlan@broadcom.com>
From: Jim Quinlan <jquinlan@broadcom.com>
The proper value of the parameter SCB_MAX_BURST_SIZE varies per chip. The
2711 family requires 128B whereas other devices can employ 512. The
assignment is complicated by the fact that the values for this two-bit
field have different meanings;
Value Type_Generic Type_7278
00 Reserved 128B
01 128B 256B
10 256B 512B
11 512B Reserved
Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
---
drivers/pci/controller/pcie-brcmstb.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 9930419e3ac2..131cf0a51398 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -53,7 +53,7 @@
#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
-#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_128 0x0
+
#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x07c00000
#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x0000001f
@@ -848,7 +848,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
int num_out_wins = 0;
u16 nlw, cls, lnksta;
int i, ret, memc;
- u32 tmp, aspm_support;
+ u32 tmp, burst, aspm_support;
/* Reset the bridge */
brcm_pcie_bridge_sw_init_set(pcie, 1);
@@ -864,10 +864,22 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
/* Wait for SerDes to be stable */
usleep_range(100, 200);
+ /*
+ * SCB_MAX_BURST_SIZE is a two bit field. For GENERIC chips it
+ * is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it
+ * is encoded as 0=Rsvd, 1=128, 2=256, 3=512.
+ */
+ if (pcie->type == BCM2711)
+ burst = 0x0; /* 128B */
+ else if (pcie->type == BCM7278)
+ burst = 0x3; /* 512 bytes */
+ else
+ burst = 0x2; /* 512 bytes */
+
/* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK);
u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK);
- u32p_replace_bits(&tmp, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_128,
+ u32p_replace_bits(&tmp, burst,
PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK);
writel(tmp, base + PCIE_MISC_MISC_CTRL);
--
2.17.1
next prev parent reply other threads:[~2020-06-03 19:21 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-03 19:20 [PATCH v3 00/13] PCI: brcmstb: enable PCIe for STB chips Jim Quinlan
2020-06-03 19:20 ` [PATCH v3 01/13] PCI: brcmstb: PCIE_BRCMSTB depends on ARCH_BRCMSTB Jim Quinlan
2020-06-03 19:20 ` [PATCH v3 02/13] ata: ahci_brcm: Fix use of BCM7216 reset controller Jim Quinlan
2020-06-04 2:57 ` Florian Fainelli
2020-06-03 19:20 ` [PATCH v3 03/13] dt-bindings: PCI: Add bindings for more Brcmstb chips Jim Quinlan
2020-06-03 19:20 ` [PATCH v3 04/13] PCI: brcmstb: Add bcm7278 reigister info Jim Quinlan
2020-06-03 20:28 ` Florian Fainelli
2020-06-03 19:20 ` [PATCH v3 05/13] PCI: brcmstb: Add suspend and resume pm_ops Jim Quinlan
2020-06-03 20:24 ` Bjorn Helgaas
2020-06-03 19:20 ` [PATCH v3 06/13] PCI: brcmstb: Add bcm7278 PERST support Jim Quinlan
2020-06-03 20:28 ` Florian Fainelli
2020-06-03 19:20 ` [PATCH v3 07/13] PCI: brcmstb: Add control of rescal reset Jim Quinlan
2020-06-03 20:30 ` Florian Fainelli
2020-06-03 19:20 ` [PATCH v3 08/13] of: Include a dev param in of_dma_get_range() Jim Quinlan
2020-06-03 19:20 ` [PATCH v3 10/13] PCI: brcmstb: Set internal memory viewport sizes Jim Quinlan
2020-06-03 20:33 ` Florian Fainelli
2020-06-03 19:20 ` [PATCH v3 11/13] PCI: brcmstb: Accommodate MSI for older chips Jim Quinlan
2020-06-04 2:56 ` Florian Fainelli
2020-06-03 19:20 ` Jim Quinlan [this message]
2020-06-03 20:06 ` [PATCH v3 12/13] PCI: brcmstb: Set bus max burst size by chip type Florian Fainelli
2020-06-03 19:20 ` [PATCH v3 13/13] PCI: brcmstb: Add bcm7211, bcm7216, bcm7445, bcm7278 to match list Jim Quinlan
2020-06-03 20:02 ` Florian Fainelli
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