From: Kyung Min Park <kyung.min.park@intel.com>
To: x86@kernel.org, linux-kernel@vger.kernel.org
Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
hpa@zytor.com, gregkh@linuxfoundation.org, ak@linux.intel.com,
dave.hansen@intel.com, tony.luck@intel.com,
ravi.v.shankar@intel.com, ricardo.neri@intel.com
Subject: [RFC PATCH 3/3] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions
Date: Wed, 10 Jun 2020 13:07:01 -0700 [thread overview]
Message-ID: <20200610200701.16757-4-kyung.min.park@intel.com> (raw)
In-Reply-To: <20200610200701.16757-1-kyung.min.park@intel.com>
Intel TSX suspend load tracking instructions aim to give a way to
choose which memory accesses do not need to be tracked in the TSX
read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK
for enumeration.
A processor supports Intel TSX suspend load address tracking if
CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK, XRESLDTRK
are available when this feature is present.
The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo.
Detailed information on the instructions and CPUID feature flag TSXLDTRK
can be found in the latest Intel Architecture Instruction Set Extensions
and Future Features Programming Reference and Intel 64 and IA-32
Architectures Software Developer's Manual.
Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
---
arch/x86/include/asm/cpufeatures.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index cd9b1ec022ec..8d850d58ea3b 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -365,6 +365,7 @@
#define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */
#define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */
#define X86_FEATURE_SERIALIZE (18*32+14) /* SERIALIZE instruction */
+#define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */
#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
--
2.17.1
next prev parent reply other threads:[~2020-06-10 20:21 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-10 20:06 [RFC PATCH 0/3] Add Documentation for /proc/cpuinfo flags Kyung Min Park
2020-06-10 20:06 ` [RFC PATCH 1/3] Documentation/x86: Add documentation for /proc/cpuinfo feature flags Kyung Min Park
2020-06-15 18:15 ` Borislav Petkov
2020-06-15 18:31 ` Luck, Tony
2020-06-15 18:37 ` Dave Hansen
2020-06-15 18:40 ` gregkh
2020-06-15 23:44 ` Kyung Min Park
2020-06-10 20:07 ` [RFC PATCH 2/3] x86/cpufeatures: Add enumeration for SERIALIZE instruction Kyung Min Park
2020-06-10 20:07 ` Kyung Min Park [this message]
2020-06-10 20:35 ` [RFC PATCH 0/3] Add Documentation for /proc/cpuinfo flags Borislav Petkov
2020-06-11 14:05 ` Dave Hansen
2020-06-11 5:34 ` Greg KH
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