From: Greentime Hu <greentime.hu@sifive.com>
To: greentime.hu@sifive.com, oleg@redhat.com,
guoren@linux.alibaba.com, vincent.chen@sifive.com,
paul.walmsley@sifive.com, palmerdabbelt@google.com,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 07/13] riscv: Add has_vector/riscv_vsize to save vector features.
Date: Fri, 12 Jun 2020 15:09:56 +0800 [thread overview]
Message-ID: <02932e625077902209ab9967735607f6054cd4d6.1591344965.git.greentime.hu@sifive.com> (raw)
In-Reply-To: <cover.1591344965.git.greentime.hu@sifive.com>
This patch is used to detect vector support status of CPU and use
riscv_vsize to save the size of all the vector registers. It assumes
all harts has the same capabilities in SMP system.
[guoren@linux.alibaba.com: add has_vector checking]
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
---
arch/riscv/kernel/cpufeature.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index c8527d770c98..9b02d8b069e3 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -16,6 +16,10 @@ unsigned long elf_hwcap __read_mostly;
#ifdef CONFIG_FPU
bool has_fpu __read_mostly;
#endif
+#ifdef CONFIG_VECTOR
+bool has_vector __read_mostly;
+unsigned long riscv_vsize __read_mostly;
+#endif
void riscv_fill_hwcap(void)
{
@@ -73,4 +77,12 @@ void riscv_fill_hwcap(void)
if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
has_fpu = true;
#endif
+
+#ifdef CONFIG_VECTOR
+ if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
+ has_vector = true;
+ /* There are 32 vector registers with vlenb length. */
+ riscv_vsize = csr_read(CSR_VLENB) * 32;
+ }
+#endif
}
--
2.27.0
next prev parent reply other threads:[~2020-06-12 7:10 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-12 7:09 [PATCH v6 00/13] riscv: Add vector ISA support Greentime Hu
2020-06-12 7:09 ` [PATCH 01/13] ptrace: Use regset_size() for dynamic regset Greentime Hu
2020-06-12 7:09 ` [PATCH 02/13] riscv: Separate patch for cflags and aflags Greentime Hu
2020-06-12 7:09 ` [PATCH 03/13] riscv: Rename __switch_to_aux -> fpu Greentime Hu
2020-06-12 7:09 ` [PATCH 04/13] riscv: Extending cpufeature.c to detect V-extension Greentime Hu
2020-06-12 7:09 ` [PATCH 05/13] riscv: Add new csr defines related to vector extension Greentime Hu
2020-06-12 7:09 ` [PATCH 06/13] riscv: Add vector feature to compile Greentime Hu
2020-06-12 7:09 ` Greentime Hu [this message]
2020-06-12 7:09 ` [PATCH 08/13] riscv: Reset vector register Greentime Hu
2020-06-12 7:09 ` [PATCH 09/13] riscv: Add vector struct and assembler definitions Greentime Hu
2020-06-12 7:09 ` [PATCH 10/13] riscv: Add task switch support for vector Greentime Hu
2020-06-12 7:10 ` [PATCH 11/13] riscv: Add ptrace vector support Greentime Hu
2020-06-12 7:10 ` [PATCH 12/13] riscv: Add sigcontext save/restore for vector Greentime Hu
2020-06-12 7:10 ` [PATCH 13/13] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu
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