From: Alex Elder <elder@linaro.org>
To: davem@davemloft.net, kuba@kernel.org
Cc: evgreen@chromium.org, subashab@codeaurora.org,
cpratapa@codeaurora.org, bjorn.andersson@linaro.org,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH net-next 3/5] net: ipa: mode register is TX only
Date: Mon, 29 Jun 2020 16:49:17 -0500 [thread overview]
Message-ID: <20200629214919.1196017-4-elder@linaro.org> (raw)
In-Reply-To: <20200629214919.1196017-1-elder@linaro.org>
The INIT_MODE endpoint configuration register is only valid for TX
endpoints. Rather than writing a zero to that register for RX
endpoints, avoid writing the register at all.
Add assertion comments communicating that TX endpoints are assumed
for the DEAGGR and SEQ endpoint configuration registers to be
consistent.
Signed-off-by: Alex Elder <elder@linaro.org>
---
drivers/net/ipa/ipa_endpoint.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c
index 0c2bec166066..ee8fc22c3abc 100644
--- a/drivers/net/ipa/ipa_endpoint.c
+++ b/drivers/net/ipa/ipa_endpoint.c
@@ -543,7 +543,9 @@ static void ipa_endpoint_init_mode(struct ipa_endpoint *endpoint)
u32 offset = IPA_REG_ENDP_INIT_MODE_N_OFFSET(endpoint->endpoint_id);
u32 val;
- if (endpoint->toward_ipa && endpoint->data->dma_mode) {
+ /* assert(endpoint->toward_ipa); */
+
+ if (endpoint->data->dma_mode) {
enum ipa_endpoint_name name = endpoint->data->dma_endpoint;
u32 dma_endpoint_id;
@@ -554,7 +556,7 @@ static void ipa_endpoint_init_mode(struct ipa_endpoint *endpoint)
} else {
val = u32_encode_bits(IPA_BASIC, MODE_FMASK);
}
- /* Other bitfields unspecified (and 0) */
+ /* All other bits unspecified (and 0) */
iowrite32(val, endpoint->ipa->reg_virt + offset);
}
@@ -702,6 +704,8 @@ static void ipa_endpoint_init_deaggr(struct ipa_endpoint *endpoint)
u32 offset = IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(endpoint->endpoint_id);
u32 val = 0;
+ /* assert(endpoint->toward_ipa); */
+
/* DEAGGR_HDR_LEN is 0 */
/* PACKET_OFFSET_VALID is 0 */
/* PACKET_OFFSET_LOCATION is ignored (not valid) */
@@ -716,6 +720,8 @@ static void ipa_endpoint_init_seq(struct ipa_endpoint *endpoint)
u32 seq_type = endpoint->seq_type;
u32 val = 0;
+ /* assert(endpoint->toward_ipa); */
+
/* Sequencer type is made up of four nibbles */
val |= u32_encode_bits(seq_type & 0xf, HPS_SEQ_TYPE_FMASK);
val |= u32_encode_bits((seq_type >> 4) & 0xf, DPS_SEQ_TYPE_FMASK);
@@ -1303,6 +1309,7 @@ static void ipa_endpoint_program(struct ipa_endpoint *endpoint)
ipa_endpoint_init_aggr(endpoint);
ipa_endpoint_init_deaggr(endpoint);
ipa_endpoint_init_seq(endpoint);
+ ipa_endpoint_init_mode(endpoint);
} else {
if (endpoint->ipa->version == IPA_VERSION_3_5_1)
(void)ipa_endpoint_program_suspend(endpoint, false);
@@ -1312,7 +1319,6 @@ static void ipa_endpoint_program(struct ipa_endpoint *endpoint)
}
ipa_endpoint_init_cfg(endpoint);
ipa_endpoint_init_hdr(endpoint);
- ipa_endpoint_init_mode(endpoint);
ipa_endpoint_status(endpoint);
}
--
2.25.1
next prev parent reply other threads:[~2020-06-29 21:50 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-29 21:49 [PATCH net-next 0/5] net: ipa: endpoint configuration updates Alex Elder
2020-06-29 21:49 ` [PATCH net-next 1/5] net: ipa: head-of-line block registers are RX only Alex Elder
2020-06-30 0:35 ` Jakub Kicinski
2020-06-30 1:01 ` Alex Elder
2020-06-30 1:03 ` David Miller
2020-06-30 1:09 ` Alex Elder
2020-06-30 19:21 ` David Miller
2020-06-30 22:41 ` Alex Elder
2020-06-30 22:49 ` David Miller
2020-06-29 21:49 ` [PATCH net-next 2/5] net: ipa: metadata_mask register is " Alex Elder
2020-06-29 21:49 ` Alex Elder [this message]
2020-06-29 21:49 ` [PATCH net-next 4/5] net: ipa: clarify endpoint register macro constraints Alex Elder
2020-06-29 21:49 ` [PATCH net-next 5/5] net: ipa: HOL_BLOCK_EN_FMASK is a 1-bit mask Alex Elder
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