From: Matheus Castello <matheus@castello.eng.br>
To: afaerber@suse.de, manivannan.sadhasivam@linaro.org
Cc: robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-actions@lists.infradead.org,
Matheus Castello <matheus@castello.eng.br>
Subject: [PATCH v1] arm64: dts: actions: Fix smp Bringing up secondary CPUs
Date: Sun, 5 Jul 2020 16:19:44 -0300 [thread overview]
Message-ID: <20200705191944.404933-1-matheus@castello.eng.br> (raw)
Change the enable-method to fix the failed to boot errors:
[ 0.040330] smp: Bringing up secondary CPUs ...
[ 0.040683] psci: failed to boot CPU1 (-22)
[ 0.040691] CPU1: failed to boot: -22
[ 0.041062] psci: failed to boot CPU2 (-22)
[ 0.041071] CPU2: failed to boot: -22
[ 0.041408] psci: failed to boot CPU3 (-22)
[ 0.041417] CPU3: failed to boot: -22
[ 0.041443] smp: Brought up 1 node, 1 CPU
[ 0.041451] SMP: Total of 1 processors activated.
Tested on Caninos Labrador v3 based on Actions Semi S700.
Signed-off-by: Matheus Castello <matheus@castello.eng.br>
---
arch/arm64/boot/dts/actions/s700.dtsi | 33 +++++++++++++++++++--------
1 file changed, 23 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi
index 2006ad5424fa..b28dbbcad27b 100644
--- a/arch/arm64/boot/dts/actions/s700.dtsi
+++ b/arch/arm64/boot/dts/actions/s700.dtsi
@@ -14,37 +14,50 @@ / {
#size-cells = <2>;
cpus {
- #address-cells = <2>;
+ #address-cells = <1>;
#size-cells = <0>;
-
+
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
- reg = <0x0 0x0>;
- enable-method = "psci";
+ reg = <0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x1f000020>;
+ next-level-cache = <&L2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
- reg = <0x0 0x1>;
- enable-method = "psci";
+ reg = <0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x1f000020>;
+ next-level-cache = <&L2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
- reg = <0x0 0x2>;
- enable-method = "psci";
+ reg = <0x2>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x1f000020>;
+ next-level-cache = <&L2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
- reg = <0x0 0x3>;
- enable-method = "psci";
+ reg = <0x3>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x1f000020>;
+ next-level-cache = <&L2>;
};
};
+
+ L2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
reserved-memory {
#address-cells = <2>;
--
2.27.0
next reply other threads:[~2020-07-05 19:44 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-05 19:19 Matheus Castello [this message]
2020-07-05 21:11 ` [PATCH v1] arm64: dts: actions: Fix smp Bringing up secondary CPUs Helen Koike
2020-07-05 22:09 ` Andreas Färber
2020-07-05 22:42 ` Matheus Castello
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