From: Florian Fainelli <f.fainelli@gmail.com>
To: linux-kernel@vger.kernel.org
Cc: Florian Fainelli <f.fainelli@gmail.com>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM
BCM7XXX ARM ARCHITECTURE),
devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND
FLATTENED DEVICE TREE BINDINGS),
linux-mips@vger.kernel.org (open list:BROADCOM BMIPS MIPS
ARCHITECTURE),
linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM
BCM7XXX ARM ARCHITECTURE)
Subject: [PATCH 6/6] irqchip/brcmstb-l2: Match UPG_AUX_AON_INTR2 compatible
Date: Thu, 9 Jul 2020 15:30:16 -0700 [thread overview]
Message-ID: <20200709223016.989-7-f.fainelli@gmail.com> (raw)
In-Reply-To: <20200709223016.989-1-f.fainelli@gmail.com>
The UPG_AUX_AON_INTR2 Level 2 interrupt controller node is defined with
the "brcm,upg-aux-aon-l2-intc" compatible string in Device Tree and
behaves as an edge triggered standard Broadcom STB L2 interrupt
controller.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/irqchip/irq-brcmstb-l2.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c
index b10fe5042a2f..cdd6a42d4efa 100644
--- a/drivers/irqchip/irq-brcmstb-l2.c
+++ b/drivers/irqchip/irq-brcmstb-l2.c
@@ -278,6 +278,8 @@ static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init);
IRQCHIP_DECLARE(brcmstb_hif_spi_l2_intc, "brcm,hif-spi-l2-intc",
brcmstb_l2_edge_intc_of_init);
+IRQCHIP_DECLARE(brcmstb_upg_aux_aon_l2_intc, "brcm,upg-aux-aon-l2-intc",
+ brcmstb_l2_edge_intc_of_init);
static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
struct device_node *parent)
--
2.17.1
next prev parent reply other threads:[~2020-07-09 22:31 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-09 22:30 [PATCH 0/6] irqchip: Broadcom STB interrupt controller updates Florian Fainelli
2020-07-09 22:30 ` [PATCH 1/6] irqchip/bcm7120-l2: Set controller as wake-up source Florian Fainelli
2020-07-09 22:30 ` [PATCH 2/6] irqchip/brcmstb-l2: " Florian Fainelli
2020-07-09 22:30 ` [PATCH 3/6] dt-bindings: interrupt-controller: Document Broadcom STB HIF L2 Florian Fainelli
2020-07-09 22:30 ` [PATCH 4/6] irqchip/brcmstb-l2: Match HIF_SPI_INTR2 compatible Florian Fainelli
2020-07-09 22:30 ` [PATCH 5/6] dt-bindings: interrupt-controller: Document UPG auxiliary L2 Florian Fainelli
2020-07-09 22:30 ` Florian Fainelli [this message]
2020-07-17 12:48 ` [PATCH 0/6] irqchip: Broadcom STB interrupt controller updates Marc Zyngier
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