MIPS: Replace HTTP links with HTTPS ones
diff mbox series

Message ID 20200713085243.32566-1-grandmaster@al2klimov.de
State New
Headers show
Series
  • MIPS: Replace HTTP links with HTTPS ones
Related show

Commit Message

Alexander A. Klimov July 13, 2020, 8:52 a.m. UTC
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.

Deterministic algorithm:
For each file:
  If not .svg:
    For each line:
      If doesn't contain `\bxmlns\b`:
        For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
	  If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
            If both the HTTP and HTTPS versions
            return 200 OK and serve the same content:
              Replace HTTP with HTTPS.

Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
---
 Continuing my work started at 93431e0607e5.
 See also: git log --oneline '--author=Alexander A. Klimov <grandmaster@al2klimov.de>' v5.7..master
 (Actually letting a shell for loop submit all this stuff for me.)

 If there are any URLs to be removed completely or at least not just HTTPSified:
 Just clearly say so and I'll *undo my change*.
 See also: https://lkml.org/lkml/2020/6/27/64

 If there are any valid, but yet not changed URLs:
 See: https://lkml.org/lkml/2020/6/26/837

 If you apply the patch, please let me know.

 Sorry again to all maintainers who complained about subject lines.
 Now I realized that you want an actually perfect prefixes,
 not just subsystem ones.
 I tried my best...
 And yes, *I could* (at least half-)automate it.
 Impossible is nothing! :)


 arch/mips/Kconfig           | 4 ++--
 arch/mips/include/asm/war.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

Comments

Jiaxun Yang July 14, 2020, 6:45 a.m. UTC | #1
在 2020/7/13 16:52, Alexander A. Klimov 写道:
> Rationale:
> Reduces attack surface on kernel devs opening the links for MITM
> as HTTPS traffic is much harder to manipulate.
>
> Deterministic algorithm:
> For each file:
>    If not .svg:
>      For each line:
>        If doesn't contain `\bxmlns\b`:
>          For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
> 	  If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
>              If both the HTTP and HTTPS versions
>              return 200 OK and serve the same content:
>                Replace HTTP with HTTPS.
>
> Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
> ---
>   Continuing my work started at 93431e0607e5.
>   See also: git log --oneline '--author=Alexander A. Klimov <grandmaster@al2klimov.de>' v5.7..master
>   (Actually letting a shell for loop submit all this stuff for me.)
>
>   If there are any URLs to be removed completely or at least not just HTTPSified:
>   Just clearly say so and I'll *undo my change*.
>   See also: https://lkml.org/lkml/2020/6/27/64
>
>   If there are any valid, but yet not changed URLs:
>   See: https://lkml.org/lkml/2020/6/26/837
>
>   If you apply the patch, please let me know.
>
>   Sorry again to all maintainers who complained about subject lines.
>   Now I realized that you want an actually perfect prefixes,
>   not just subsystem ones.
>   I tried my best...
>   And yes, *I could* (at least half-)automate it.
>   Impossible is nothing! :)
>
>
>   arch/mips/Kconfig           | 4 ++--
>   arch/mips/include/asm/war.h | 2 +-
>   2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 6fee1a133e9d..bdd073a0a67e 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -2393,7 +2393,7 @@ config MIPS_MT_SMP
>   	  on cores with the MT ASE and uses the available VPEs to implement
>   	  virtual processors which supports SMP. This is equivalent to the
>   	  Intel Hyperthreading feature. For further information go to
> -	  <http://www.imgtec.com/mips/mips-multithreading.asp>.
> +	  <https://www.imgtec.com/mips/mips-multithreading.asp>.

All MIPS content have been removed from IMGTEC's site, we'd better remove
this link?

- Jiaxun
Thomas Bogendoerfer July 16, 2020, 1:56 p.m. UTC | #2
On Wed, Jul 15, 2020 at 12:07:55PM +0200, Aleksandar Markovic wrote:
> On Tuesday, July 14, 2020, Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
> > 在 2020/7/13 16:52, Alexander A. Klimov 写道:
> >>           virtual processors which supports SMP. This is equivalent to the
> >>           Intel Hyperthreading feature. For further information go to
> >> -         <http://www.imgtec.com/mips/mips-multithreading.asp>.
> >> +         <https://www.imgtec.com/mips/mips-multithreading.asp>.
> >>
> >
> > All MIPS content have been removed from IMGTEC's site, we'd better remove
> > this link?
> >
> >
> Perhaps it is better to replace it with:
> 
> https://www.mips.com/products/architectures/ase/multi-threading/
> 
> ?

yes, looks better.

Thomas.

Patch
diff mbox series

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 6fee1a133e9d..bdd073a0a67e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2393,7 +2393,7 @@  config MIPS_MT_SMP
 	  on cores with the MT ASE and uses the available VPEs to implement
 	  virtual processors which supports SMP. This is equivalent to the
 	  Intel Hyperthreading feature. For further information go to
-	  <http://www.imgtec.com/mips/mips-multithreading.asp>.
+	  <https://www.imgtec.com/mips/mips-multithreading.asp>.
 
 config MIPS_MT
 	bool
@@ -2825,7 +2825,7 @@  config SMP
 	  Y to "Enhanced Real Time Clock Support", below.
 
 	  See also the SMP-HOWTO available at
-	  <http://www.tldp.org/docs.html#howto>.
+	  <https://www.tldp.org/docs.html#howto>.
 
 	  If you don't know what to do here, say N.
 
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index 1eedd596a064..e43f800e662d 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -121,7 +121,7 @@ 
  * operate correctly if the internal data cache refill buffer is empty.	 These
  * CACHE instructions should be separated from any potential data cache miss
  * by a load instruction to an uncached address to empty the response buffer."
- * (Revision 2.0 device errata from IDT available on http://www.idt.com/
+ * (Revision 2.0 device errata from IDT available on https://www.idt.com/
  * in .pdf format.)
  */
 #ifndef R4600_V2_HIT_CACHEOP_WAR