From: "Saheed O. Bolarinwa" <refactormyself@gmail.com>
To: skhan@linuxfoundation.org, linux-pci@vger.kernel.org,
linux-kernel-mentees@lists.linuxfoundation.org,
linux-kernel@vger.kernel.org,
QCA ath9k Development <ath9k-devel@qca.qualcomm.com>,
linux-wireless@vger.kernel.org, netdev@vger.kernel.org
Cc: Bolarinwa Olayemi Saheed <refactormyself@gmail.com>,
Kalle Valo <kvalo@codeaurora.org>
Subject: [PATCH 3/14 v3] ath9k: Check the return value of pcie_capability_read_*()
Date: Mon, 13 Jul 2020 19:55:26 +0200 [thread overview]
Message-ID: <20200713175529.29715-2-refactormyself@gmail.com> (raw)
In-Reply-To: <20200713175529.29715-1-refactormyself@gmail.com>
From: Bolarinwa Olayemi Saheed <refactormyself@gmail.com>
On failure pcie_capability_read_dword() sets it's last parameter, val
to 0. However, with Patch 14/14, it is possible that val is set to ~0 on
failure. This would introduce a bug because (x & x) == (~0 & x).
This bug can be avoided without changing the function's behaviour if the
return value of pcie_capability_read_dword is checked to confirm success.
Check the return value of pcie_capability_read_dword() to ensure success.
Suggested-by: Bjorn Helgaas <bjorn@helgaas.com>
Signed-off-by: Bolarinwa Olayemi Saheed <refactormyself@gmail.com>
---
drivers/net/wireless/ath/ath9k/pci.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index f3461b193c7a..cff9af3af38d 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -825,6 +825,7 @@ static void ath_pci_aspm_init(struct ath_common *common)
struct pci_dev *pdev = to_pci_dev(sc->dev);
struct pci_dev *parent;
u16 aspm;
+ int ret;
if (!ah->is_pciexpress)
return;
@@ -866,8 +867,8 @@ static void ath_pci_aspm_init(struct ath_common *common)
if (AR_SREV_9462(ah))
pci_read_config_dword(pdev, 0x70c, &ah->config.aspm_l1_fix);
- pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm);
- if (aspm & (PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1)) {
+ ret = pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm);
+ if (!ret && (aspm & (PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1))) {
ah->aspm_enabled = true;
/* Initialize PCIe PM and SERDES registers. */
ath9k_hw_configpcipowersave(ah, false);
--
2.18.2
next prev parent reply other threads:[~2020-07-13 16:55 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-13 17:55 [PATCH 1/14 v3] IB/hfi1: Check the return value of pcie_capability_read_*() Saheed O. Bolarinwa
2020-07-13 17:09 ` Jason Gunthorpe
2020-07-13 17:55 ` Saheed O. Bolarinwa [this message]
2020-07-20 17:09 ` [PATCH 3/14 v3] ath9k: " Kalle Valo
2020-07-13 17:55 ` [PATCH 4/14 v3] iwlegacy: " Saheed O. Bolarinwa
2020-07-15 16:47 ` Kalle Valo
2020-07-13 17:55 ` [PATCH 8/14 v3] PCI/ACPI: " Saheed O. Bolarinwa
2020-07-14 13:27 ` Rafael J. Wysocki
2020-07-13 17:55 ` [PATCH 12/14 v3] PCI/AER: " Saheed O. Bolarinwa
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