From: Swapnil Jakhade <sjakhade@cadence.com>
To: <vkoul@kernel.org>, <kishon@ti.com>, <robh+dt@kernel.org>,
<p.zabel@pengutronix.de>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>
Cc: <mparab@cadence.com>, <sjakhade@cadence.com>,
<yamonkar@cadence.com>, <tomi.valkeinen@ti.com>, <jsarha@ti.com>,
<nsekhar@ti.com>
Subject: [PATCH v1 08/13] phy: cadence-torrent: Add PHY link configuration sequences for single link
Date: Fri, 7 Aug 2020 13:46:02 +0200 [thread overview]
Message-ID: <1596800767-784-9-git-send-email-sjakhade@cadence.com> (raw)
In-Reply-To: <1596800767-784-1-git-send-email-sjakhade@cadence.com>
Add support to configure link_cmn_vals and xcvr_diag_vals in case of single
link PHY configuration.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
drivers/phy/cadence/phy-cadence-torrent.c | 44 +++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 691d4aa5b2ed..d01a44b93e99 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -1809,6 +1809,7 @@ static int cdns_torrent_phy_init(struct phy *phy)
struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
const struct cdns_torrent_data *init_data = cdns_phy->init_data;
struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
+ struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
enum cdns_torrent_phy_type phy_type = inst->phy_type;
enum cdns_torrent_ssc_mode ssc = inst->ssc_mode;
@@ -1823,6 +1824,29 @@ static int cdns_torrent_phy_init(struct phy *phy)
if (phy_type == TYPE_DP)
return cdns_torrent_dp_init(phy);
+ /* PHY configuration specific registers for single link */
+ link_cmn_vals = init_data->link_cmn_vals[phy_type][TYPE_NONE][ssc];
+ if (link_cmn_vals) {
+ reg_pairs = link_cmn_vals->reg_pairs;
+ num_regs = link_cmn_vals->num_regs;
+ regmap = cdns_phy->regmap_common_cdb;
+ for (i = 0; i < num_regs; i++)
+ regmap_write(regmap, reg_pairs[i].off,
+ reg_pairs[i].val);
+ }
+
+ xcvr_diag_vals = init_data->xcvr_diag_vals[phy_type][TYPE_NONE][ssc];
+ if (xcvr_diag_vals) {
+ reg_pairs = xcvr_diag_vals->reg_pairs;
+ num_regs = xcvr_diag_vals->num_regs;
+ for (i = 0; i < inst->num_lanes; i++) {
+ regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
+ for (j = 0; j < num_regs; j++)
+ regmap_write(regmap, reg_pairs[j].off,
+ reg_pairs[j].val);
+ }
+ }
+
/* PMA common registers configurations */
cmn_vals = init_data->cmn_vals[phy_type][TYPE_NONE][ssc];
if (cmn_vals) {
@@ -2646,6 +2670,11 @@ static const struct cdns_torrent_data cdns_map_torrent = {
.reg_offset_shift = 0x2,
.link_cmn_vals = {
[TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = NULL,
+ [EXTERNAL_SSC] = NULL,
+ [INTERNAL_SSC] = NULL,
+ },
[TYPE_SGMII] = {
[NO_SSC] = &pcie_sgmii_link_cmn_vals,
[EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
@@ -2674,6 +2703,11 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
.xcvr_diag_vals = {
[TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = NULL,
+ [EXTERNAL_SSC] = NULL,
+ [INTERNAL_SSC] = NULL,
+ },
[TYPE_SGMII] = {
[NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
[EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
@@ -2806,6 +2840,11 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
.reg_offset_shift = 0x1,
.link_cmn_vals = {
[TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = NULL,
+ [EXTERNAL_SSC] = NULL,
+ [INTERNAL_SSC] = NULL,
+ },
[TYPE_SGMII] = {
[NO_SSC] = &pcie_sgmii_link_cmn_vals,
[EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
@@ -2834,6 +2873,11 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
.xcvr_diag_vals = {
[TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = NULL,
+ [EXTERNAL_SSC] = NULL,
+ [INTERNAL_SSC] = NULL,
+ },
[TYPE_SGMII] = {
[NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
[EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
--
2.26.1
next prev parent reply other threads:[~2020-08-07 11:46 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-07 11:45 [PATCH v1 00/13] PHY: Add support for multilink configurations in Cadence Torrent PHY driver Swapnil Jakhade
2020-08-07 11:45 ` [PATCH v1 01/13] phy: cadence-torrent: Add single link PCIe support Swapnil Jakhade
2020-08-07 11:45 ` [PATCH v1 02/13] phy: cadence-torrent: Check cmn_ready assertion during PHY power on Swapnil Jakhade
2020-08-07 11:45 ` [PATCH v1 03/13] phy: cadence-torrent: Add PHY APB reset support Swapnil Jakhade
2020-08-07 11:45 ` [PATCH v1 04/13] dt-bindings: phy: Add PHY_TYPE_QSGMII definition Swapnil Jakhade
2020-08-17 22:14 ` Rob Herring
2020-08-07 11:45 ` [PATCH v1 05/13] phy: cadence-torrent: Add support for PHY multilink configuration Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 06/13] phy: cadence-torrent: Update PHY reset for " Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 07/13] phy: cadence-torrent: Add clk changes " Swapnil Jakhade
2020-08-07 11:46 ` Swapnil Jakhade [this message]
2020-08-07 11:46 ` [PATCH v1 09/13] phy: cadence-torrent: Configure PHY_PLL_CFG as part of link_cmn_vals Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 10/13] phy: cadence-torrent: Add single link SGMII/QSGMII register sequences Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 11/13] phy: cadence-torrent: Add single link USB " Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 12/13] phy: cadence-torrent: Add PCIe + USB multilink configuration Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 13/13] phy: cadence-torrent: Add USB + SGMII/QSGMII " Swapnil Jakhade
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