From: Swapnil Jakhade <sjakhade@cadence.com>
To: <vkoul@kernel.org>, <kishon@ti.com>, <robh+dt@kernel.org>,
<p.zabel@pengutronix.de>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>
Cc: <mparab@cadence.com>, <sjakhade@cadence.com>,
<yamonkar@cadence.com>, <tomi.valkeinen@ti.com>, <jsarha@ti.com>,
<nsekhar@ti.com>
Subject: [PATCH v1 02/13] phy: cadence-torrent: Check cmn_ready assertion during PHY power on
Date: Fri, 7 Aug 2020 13:45:56 +0200 [thread overview]
Message-ID: <1596800767-784-3-git-send-email-sjakhade@cadence.com> (raw)
In-Reply-To: <1596800767-784-1-git-send-email-sjakhade@cadence.com>
Check if cmn_ready is set after both PLL0 and PLL1 are locked.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
drivers/phy/cadence/phy-cadence-torrent.c | 31 ++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index a703fcb355a8..8c6e1aa93b64 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -32,6 +32,7 @@
#define NUM_PHY_TYPE 2
#define POLL_TIMEOUT_US 5000
+#define PLL_LOCK_TIMEOUT 100000
#define TORRENT_COMMON_CDB_OFFSET 0x0
@@ -183,12 +184,16 @@
#define PHY_PLL_CFG 0x000EU
/* PHY PMA common registers */
+#define PHY_PMA_CMN_CTRL1 0x0000U
#define PHY_PMA_CMN_CTRL2 0x0001U
#define PHY_PMA_PLL_RAW_CTRL 0x0003U
static const struct reg_field phy_pll_cfg =
REG_FIELD(PHY_PLL_CFG, 0, 1);
+static const struct reg_field phy_pma_cmn_ctrl_1 =
+ REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0);
+
static const struct reg_field phy_pma_cmn_ctrl_2 =
REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7);
@@ -237,6 +242,7 @@ struct cdns_torrent_phy {
struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];
struct regmap *regmap_dptx_phy_reg;
struct regmap_field *phy_pll_cfg;
+ struct regmap_field *phy_pma_cmn_ctrl_1;
struct regmap_field *phy_pma_cmn_ctrl_2;
struct regmap_field *phy_pma_pll_raw_ctrl;
struct regmap_field *phy_reset_ctrl;
@@ -1570,6 +1576,7 @@ static int cdns_torrent_phy_on(struct phy *phy)
{
struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
+ u32 read_val;
int ret;
/* Take the PHY out of reset */
@@ -1578,7 +1585,21 @@ static int cdns_torrent_phy_on(struct phy *phy)
return ret;
/* Take the PHY lane group out of reset */
- return reset_control_deassert(inst->lnk_rst);
+ reset_control_deassert(inst->lnk_rst);
+
+ /*
+ * Wait for cmn_ready assertion
+ * PHY_PMA_CMN_CTRL1[0] == 1
+ */
+ ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1,
+ read_val, read_val, 1000,
+ PLL_LOCK_TIMEOUT);
+ if (ret) {
+ dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n");
+ return ret;
+ }
+
+ return 0;
}
static int cdns_torrent_phy_off(struct phy *phy)
@@ -1643,6 +1664,14 @@ static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy)
}
cdns_phy->phy_pll_cfg = field;
+ regmap = cdns_phy->regmap_phy_pma_common_cdb;
+ field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1);
+ if (IS_ERR(field)) {
+ dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n");
+ return PTR_ERR(field);
+ }
+ cdns_phy->phy_pma_cmn_ctrl_1 = field;
+
regmap = cdns_phy->regmap_phy_pma_common_cdb;
field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2);
if (IS_ERR(field)) {
--
2.26.1
next prev parent reply other threads:[~2020-08-07 11:47 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-07 11:45 [PATCH v1 00/13] PHY: Add support for multilink configurations in Cadence Torrent PHY driver Swapnil Jakhade
2020-08-07 11:45 ` [PATCH v1 01/13] phy: cadence-torrent: Add single link PCIe support Swapnil Jakhade
2020-08-07 11:45 ` Swapnil Jakhade [this message]
2020-08-07 11:45 ` [PATCH v1 03/13] phy: cadence-torrent: Add PHY APB reset support Swapnil Jakhade
2020-08-07 11:45 ` [PATCH v1 04/13] dt-bindings: phy: Add PHY_TYPE_QSGMII definition Swapnil Jakhade
2020-08-17 22:14 ` Rob Herring
2020-08-07 11:45 ` [PATCH v1 05/13] phy: cadence-torrent: Add support for PHY multilink configuration Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 06/13] phy: cadence-torrent: Update PHY reset for " Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 07/13] phy: cadence-torrent: Add clk changes " Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 08/13] phy: cadence-torrent: Add PHY link configuration sequences for single link Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 09/13] phy: cadence-torrent: Configure PHY_PLL_CFG as part of link_cmn_vals Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 10/13] phy: cadence-torrent: Add single link SGMII/QSGMII register sequences Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 11/13] phy: cadence-torrent: Add single link USB " Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 12/13] phy: cadence-torrent: Add PCIe + USB multilink configuration Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 13/13] phy: cadence-torrent: Add USB + SGMII/QSGMII " Swapnil Jakhade
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