From: Greentime Hu <greentime.hu@sifive.com>
To: greentime.hu@sifive.com, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu,
palmer@dabbelt.com, paul.walmsley@sifive.com
Cc: Guo Ren <guoren@linux.alibaba.com>
Subject: [RFC PATCH v7 08/21] riscv: Add vector struct and assembler definitions
Date: Thu, 10 Sep 2020 16:12:03 +0800 [thread overview]
Message-ID: <4cb7ed8c6af8e1865ca817d590f06f4fb485230f.1599719352.git.greentime.hu@sifive.com> (raw)
In-Reply-To: <cover.1599719352.git.greentime.hu@sifive.com>
Add vector state context struct in struct thread and asm-offsets.c
definitions.
The vector registers will be saved in datap pointer of __riscv_v_state. It
will be dynamically allocated in kernel space. It will be put right after
the __riscv_v_state data structure in user space.
[guoren@linux.alibaba.com: first version vector porting]
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
---
arch/riscv/include/asm/processor.h | 1 +
arch/riscv/include/uapi/asm/ptrace.h | 13 +++++++++++++
arch/riscv/kernel/asm-offsets.c | 8 ++++++++
3 files changed, 22 insertions(+)
diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index bdddcd5c1b71..a66a5d4ee5ad 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -34,6 +34,7 @@ struct thread_struct {
unsigned long sp; /* Kernel mode stack */
unsigned long s[12]; /* s[0]: frame pointer */
struct __riscv_d_ext_state fstate;
+ struct __riscv_v_state vstate;
};
#define INIT_THREAD { \
diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h
index 882547f6bd5c..661b0466b850 100644
--- a/arch/riscv/include/uapi/asm/ptrace.h
+++ b/arch/riscv/include/uapi/asm/ptrace.h
@@ -77,6 +77,19 @@ union __riscv_fp_state {
struct __riscv_q_ext_state q;
};
+struct __riscv_v_state {
+ __u32 magic;
+ __u32 size;
+ unsigned long vstart;
+ unsigned long vl;
+ unsigned long vtype;
+ unsigned long vcsr;
+ void *datap;
+#if __riscv_xlen == 32
+ __u32 __padding;
+#endif
+} __attribute__((aligned(16)));
+
#endif /* __ASSEMBLY__ */
#endif /* _UAPI_ASM_RISCV_PTRACE_H */
diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c
index db203442c08f..f6fa65a6aaf0 100644
--- a/arch/riscv/kernel/asm-offsets.c
+++ b/arch/riscv/kernel/asm-offsets.c
@@ -67,6 +67,14 @@ void asm_offsets(void)
OFFSET(TASK_THREAD_F31, task_struct, thread.fstate.f[31]);
OFFSET(TASK_THREAD_FCSR, task_struct, thread.fstate.fcsr);
+ OFFSET(RISCV_V_STATE_MAGIC, __riscv_v_state, magic);
+ OFFSET(RISCV_V_STATE_SIZE, __riscv_v_state, size);
+ OFFSET(RISCV_V_STATE_VSTART, __riscv_v_state, vstart);
+ OFFSET(RISCV_V_STATE_VL, __riscv_v_state, vl);
+ OFFSET(RISCV_V_STATE_VTYPE, __riscv_v_state, vtype);
+ OFFSET(RISCV_V_STATE_VCSR, __riscv_v_state, vcsr);
+ OFFSET(RISCV_V_STATE_DATAP, __riscv_v_state, datap);
+
DEFINE(PT_SIZE, sizeof(struct pt_regs));
OFFSET(PT_EPC, pt_regs, epc);
OFFSET(PT_RA, pt_regs, ra);
--
2.28.0
next prev parent reply other threads:[~2020-09-10 8:21 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-10 8:11 [RFC PATCH v7 00/21] riscv: Add vector ISA support Greentime Hu
2020-09-10 8:11 ` [RFC PATCH v7 01/21] riscv: Separate patch for cflags and aflags Greentime Hu
2020-09-10 8:11 ` [RFC PATCH v7 02/21] riscv: Rename __switch_to_aux -> fpu Greentime Hu
2020-09-10 8:11 ` [RFC PATCH v7 03/21] riscv: Extending cpufeature.c to detect V-extension Greentime Hu
2020-09-10 8:11 ` [RFC PATCH v7 04/21] riscv: Add new csr defines related to vector extension Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 05/21] riscv: Add vector feature to compile Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 06/21] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 07/21] riscv: Reset vector register Greentime Hu
2020-09-10 8:12 ` Greentime Hu [this message]
2020-09-10 8:12 ` [RFC PATCH v7 09/21] riscv: Add task switch support for vector Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 10/21] " Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 11/21] riscv: Add ptrace vector support Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 12/21] riscv: Add sigcontext save/restore for vector Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 13/21] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 14/21] riscv: Add support for kernel mode vector Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 15/21] riscv: Use CSR_STATUS to replace sstatus in vector.S Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 16/21] riscv: Add vector extension XOR implementation Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 17/21] riscv: Initialize vector registers with proper vsetvli then it can work normally Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 18/21] riscv: Optimize vector registers initialization Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 19/21] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 20/21] riscv: Allocate space for vector registers in start_thread() Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 21/21] riscv: Optimize task switch codes of vector Greentime Hu
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