From: Greentime Hu <greentime.hu@sifive.com>
To: greentime.hu@sifive.com, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu,
palmer@dabbelt.com, paul.walmsley@sifive.com
Cc: Andrew Waterman <andrew@sifive.com>
Subject: [RFC PATCH v7 21/21] riscv: Optimize task switch codes of vector
Date: Thu, 10 Sep 2020 16:12:16 +0800 [thread overview]
Message-ID: <50eb3d9d0a92d6faa39e9fedb941863426daca76.1599719352.git.greentime.hu@sifive.com> (raw)
In-Reply-To: <cover.1599719352.git.greentime.hu@sifive.com>
This patch replacees 2 instructions with 1 instruction to do the same thing
. rs1=x0 with rd != x0 is a special form of the instruction that sets vl to
MAXVL.
Suggested-by: Andrew Waterman <andrew@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
---
arch/riscv/kernel/vector.S | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/kernel/vector.S b/arch/riscv/kernel/vector.S
index 4f0c5a166e4e..f7223c81b11a 100644
--- a/arch/riscv/kernel/vector.S
+++ b/arch/riscv/kernel/vector.S
@@ -27,8 +27,7 @@
#define x_vl t2
#define x_vcsr t3
#define incr t4
-#define m_one t5
-#define status t6
+#define status t5
ENTRY(__vstate_save)
li status, SR_VS
@@ -38,8 +37,7 @@ ENTRY(__vstate_save)
csrr x_vtype, CSR_VTYPE
csrr x_vl, CSR_VL
csrr x_vcsr, CSR_VCSR
- li m_one, -1
- vsetvli incr, m_one, e8, m8
+ vsetvli incr, x0, e8, m8
vse8.v v0, (datap)
add datap, datap, incr
vse8.v v8, (datap)
@@ -61,8 +59,7 @@ ENTRY(__vstate_restore)
li status, SR_VS
csrs CSR_STATUS, status
- li m_one, -1
- vsetvli incr, m_one, e8, m8
+ vsetvli incr, x0, e8, m8
vle8.v v0, (datap)
add datap, datap, incr
vle8.v v8, (datap)
--
2.28.0
prev parent reply other threads:[~2020-09-10 8:25 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-10 8:11 [RFC PATCH v7 00/21] riscv: Add vector ISA support Greentime Hu
2020-09-10 8:11 ` [RFC PATCH v7 01/21] riscv: Separate patch for cflags and aflags Greentime Hu
2020-09-10 8:11 ` [RFC PATCH v7 02/21] riscv: Rename __switch_to_aux -> fpu Greentime Hu
2020-09-10 8:11 ` [RFC PATCH v7 03/21] riscv: Extending cpufeature.c to detect V-extension Greentime Hu
2020-09-10 8:11 ` [RFC PATCH v7 04/21] riscv: Add new csr defines related to vector extension Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 05/21] riscv: Add vector feature to compile Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 06/21] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 07/21] riscv: Reset vector register Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 08/21] riscv: Add vector struct and assembler definitions Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 09/21] riscv: Add task switch support for vector Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 10/21] " Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 11/21] riscv: Add ptrace vector support Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 12/21] riscv: Add sigcontext save/restore for vector Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 13/21] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 14/21] riscv: Add support for kernel mode vector Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 15/21] riscv: Use CSR_STATUS to replace sstatus in vector.S Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 16/21] riscv: Add vector extension XOR implementation Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 17/21] riscv: Initialize vector registers with proper vsetvli then it can work normally Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 18/21] riscv: Optimize vector registers initialization Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 19/21] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first Greentime Hu
2020-09-10 8:12 ` [RFC PATCH v7 20/21] riscv: Allocate space for vector registers in start_thread() Greentime Hu
2020-09-10 8:12 ` Greentime Hu [this message]
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