From: Nicolin Chen <nicoleotsuka@gmail.com>
To: krzk@kernel.org, joro@8bytes.org
Cc: linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org,
linux-tegra@vger.kernel.org, jonathanh@nvidia.com,
vdumpa@nvidia.com, thierry.reding@gmail.com
Subject: [RESEND][PATCH 1/2] iommu/tegra-smmu: Fix tlb_mask
Date: Thu, 17 Sep 2020 04:31:54 -0700 [thread overview]
Message-ID: <20200917113155.13438-2-nicoleotsuka@gmail.com> (raw)
In-Reply-To: <20200917113155.13438-1-nicoleotsuka@gmail.com>
The "num_tlb_lines" might not be a power-of-2 value, being 48 on
Tegra210 for example. So the current way of calculating tlb_mask
using the num_tlb_lines is not correct: tlb_mask=0x5f in case of
num_tlb_lines=48, which will trim a setting of 0x30 (48) to 0x10.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
drivers/iommu/tegra-smmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c
index 84fdee473873..0becdbfea306 100644
--- a/drivers/iommu/tegra-smmu.c
+++ b/drivers/iommu/tegra-smmu.c
@@ -1120,7 +1120,7 @@ struct tegra_smmu *tegra_smmu_probe(struct device *dev,
BIT_MASK(mc->soc->num_address_bits - SMMU_PTE_SHIFT) - 1;
dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n",
mc->soc->num_address_bits, smmu->pfn_mask);
- smmu->tlb_mask = (smmu->soc->num_tlb_lines << 1) - 1;
+ smmu->tlb_mask = (1 << fls(smmu->soc->num_tlb_lines)) - 1;
dev_dbg(dev, "TLB lines: %u, mask: %#lx\n", smmu->soc->num_tlb_lines,
smmu->tlb_mask);
--
2.17.1
next prev parent reply other threads:[~2020-09-17 11:47 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-17 11:31 [RESEND][PATCH 0/2] iommu/tegra-smmu: Fix TLB line for Tegra210 Nicolin Chen
2020-09-17 11:31 ` Nicolin Chen [this message]
2020-09-17 11:31 ` [RESEND][PATCH 2/2] memory: tegra: Correct num_tlb_lines for tegra210 Nicolin Chen
2020-09-18 9:07 ` [RESEND][PATCH 0/2] iommu/tegra-smmu: Fix TLB line for Tegra210 Joerg Roedel
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