[2/2] MIPS: Ingenic: Fix bugs when detecting X1000E's L2 cache.
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Message ID 20200919124437.89576-3-zhouyanjie@wanyeetech.com
State New, archived
Headers show
Series
  • Repair X1000E SoC L2 cache capacity detection.
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Commit Message

周琰杰 (Zhou Yanjie) Sept. 19, 2020, 12:44 p.m. UTC
Fix bugs when detecting L2 cache sets value and ways value.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
 arch/mips/mm/sc-mips.c | 1 +
 1 file changed, 1 insertion(+)

Patch
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diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 97dc0511e63f..145b39ecb246 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -235,6 +235,7 @@  static inline int __init mips_sc_probe(void)
 		 * According to config2 it would be 5-ways and 512-sets,
 		 * but that is contradicted by all documentation.
 		 */
+		case MACH_INGENIC_X1000E:
 		case MACH_INGENIC_X1000:
 			c->scache.sets = 256;
 			c->scache.ways = 4;