From: "tip-bot2 for Krish Sadhukhan" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Krish Sadhukhan <krish.sadhukhan@oracle.com>,
Borislav Petkov <bp@suse.de>, Paolo Bonzini <pbonzini@redhat.com>,
x86 <x86@kernel.org>, LKML <linux-kernel@vger.kernel.org>
Subject: [tip: x86/cpu] KVM: SVM: Don't flush cache if hardware enforces cache coherency across encryption domains
Date: Sat, 19 Sep 2020 18:57:27 -0000 [thread overview]
Message-ID: <160054184758.15536.15665221112789518623.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20200917212038.5090-4-krish.sadhukhan@oracle.com>
The following commit has been merged into the x86/cpu branch of tip:
Commit-ID: e1ebb2b49048c4767cfa0d8466f9c701e549fa5e
Gitweb: https://git.kernel.org/tip/e1ebb2b49048c4767cfa0d8466f9c701e549fa5e
Author: Krish Sadhukhan <krish.sadhukhan@oracle.com>
AuthorDate: Thu, 17 Sep 2020 21:20:38
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Sat, 19 Sep 2020 20:46:59 +02:00
KVM: SVM: Don't flush cache if hardware enforces cache coherency across encryption domains
In some hardware implementations, coherency between the encrypted and
unencrypted mappings of the same physical page in a VM is enforced. In
such a system, it is not required for software to flush the VM's page
from all CPU caches in the system prior to changing the value of the
C-bit for the page.
So check that bit before flushing the cache.
Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Link: https://lkml.kernel.org/r/20200917212038.5090-4-krish.sadhukhan@oracle.com
---
arch/x86/kvm/svm/sev.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c
index 402dc42..567792f 100644
--- a/arch/x86/kvm/svm/sev.c
+++ b/arch/x86/kvm/svm/sev.c
@@ -384,7 +384,8 @@ static void sev_clflush_pages(struct page *pages[], unsigned long npages)
uint8_t *page_virtual;
unsigned long i;
- if (npages == 0 || pages == NULL)
+ if (this_cpu_has(X86_FEATURE_SME_COHERENT) || npages == 0 ||
+ pages == NULL)
return;
for (i = 0; i < npages; i++) {
prev parent reply other threads:[~2020-09-19 18:57 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-17 21:20 [PATCH 0/3 v4] x86: AMD: Don't flush cache if hardware enforces cache coherency across encryption domains Krish Sadhukhan
2020-09-17 21:20 ` [PATCH 1/3 v4] x86: AMD: Add hardware-enforced cache coherency as a CPUID feature Krish Sadhukhan
2020-09-18 7:58 ` [tip: x86/cpu] x86/cpu: " tip-bot2 for Krish Sadhukhan
2020-09-18 9:03 ` tip-bot2 for Krish Sadhukhan
2020-09-17 21:20 ` [PATCH 2/3 v4] x86: AMD: Don't flush cache if hardware enforces cache coherency across encryption domnains Krish Sadhukhan
2020-09-18 7:58 ` [tip: x86/cpu] x86/mm/pat: " tip-bot2 for Krish Sadhukhan
2020-09-18 9:03 ` tip-bot2 for Krish Sadhukhan
2020-09-17 21:20 ` [PATCH 3/3 v4] KVM: SVM: Don't flush cache if hardware enforces cache coherency across encryption domains Krish Sadhukhan
2020-09-18 7:56 ` Borislav Petkov
2020-09-19 15:18 ` Paolo Bonzini
2020-09-19 18:57 ` tip-bot2 for Krish Sadhukhan [this message]
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