From: Kai-Heng Feng <kai.heng.feng@canonical.com>
To: jeffrey.t.kirsher@intel.com
Cc: andrew@lunn.ch, Kai-Heng Feng <kai.heng.feng@canonical.com>,
"David S. Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>,
intel-wired-lan@lists.osuosl.org (moderated list:INTEL ETHERNET
DRIVERS), netdev@vger.kernel.org (open list:NETWORKING DRIVERS),
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v2] e1000e: Increase iteration on polling MDIC ready bit
Date: Thu, 24 Sep 2020 23:09:58 +0800 [thread overview]
Message-ID: <20200924150958.18016-1-kai.heng.feng@canonical.com> (raw)
In-Reply-To: <20200923074751.10527-1-kai.heng.feng@canonical.com>
We are seeing the following error after S3 resume:
[ 704.746874] e1000e 0000:00:1f.6 eno1: Setting page 0x6020
[ 704.844232] e1000e 0000:00:1f.6 eno1: MDI Write did not complete
[ 704.902817] e1000e 0000:00:1f.6 eno1: Setting page 0x6020
[ 704.903075] e1000e 0000:00:1f.6 eno1: reading PHY page 769 (or 0x6020 shifted) reg 0x17
[ 704.903281] e1000e 0000:00:1f.6 eno1: Setting page 0x6020
[ 704.903486] e1000e 0000:00:1f.6 eno1: writing PHY page 769 (or 0x6020 shifted) reg 0x17
[ 704.943155] e1000e 0000:00:1f.6 eno1: MDI Error
...
[ 705.108161] e1000e 0000:00:1f.6 eno1: Hardware Error
As Andrew Lunn pointed out, MDIO has nothing to do with phy, and indeed
increase polling iteration can resolve the issue.
While at it, also move the delay to the end of loop, to potentially save
50 us.
Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
---
v2:
- Increase polling iteration instead of powering down the phy.
drivers/net/ethernet/intel/e1000e/phy.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/intel/e1000e/phy.c b/drivers/net/ethernet/intel/e1000e/phy.c
index e11c877595fb..72968a01164b 100644
--- a/drivers/net/ethernet/intel/e1000e/phy.c
+++ b/drivers/net/ethernet/intel/e1000e/phy.c
@@ -203,11 +203,12 @@ s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
* Increasing the time out as testing showed failures with
* the lower time out
*/
- for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
- udelay(50);
+ for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 10); i++) {
mdic = er32(MDIC);
if (mdic & E1000_MDIC_READY)
break;
+
+ udelay(50);
}
if (!(mdic & E1000_MDIC_READY)) {
e_dbg("MDI Write did not complete\n");
--
2.17.1
next prev parent reply other threads:[~2020-09-24 15:10 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-23 7:47 [PATCH] e1000e: Power cycle phy on PM resume Kai-Heng Feng
2020-09-23 12:17 ` Andrew Lunn
2020-09-23 14:44 ` Kai-Heng Feng
2020-09-23 15:37 ` Andrew Lunn
2020-09-24 12:50 ` Kai-Heng Feng
2020-09-23 13:28 ` [Intel-wired-lan] " Paul Menzel
2020-09-23 14:46 ` Kai-Heng Feng
2020-09-23 15:02 ` Paul Menzel
2020-09-23 19:28 ` Andrew Lunn
2020-09-24 13:02 ` Paul Menzel
2020-09-24 15:09 ` Kai-Heng Feng [this message]
2020-09-24 15:32 ` [Intel-wired-lan] [PATCH v2] e1000e: Increase iteration on polling MDIC ready bit Paul Menzel
2020-09-24 16:04 ` Andrew Lunn
2020-09-24 15:53 ` Andrew Lunn
2020-09-24 16:04 ` Kai-Heng Feng
2020-09-25 8:50 ` David Laight
2020-09-25 13:29 ` Andrew Lunn
2020-09-26 10:08 ` David Laight
2020-09-24 16:45 ` [PATCH v3] " Kai-Heng Feng
2020-09-24 19:57 ` Andrew Lunn
2020-09-25 3:57 ` Kai-Heng Feng
2020-09-25 5:16 ` [Intel-wired-lan] " Paul Menzel
2020-09-28 8:36 ` [PATCH v4] e1000e: Increase polling timeout on " Kai-Heng Feng
2020-09-29 13:08 ` [Intel-wired-lan] " Neftin, Sasha
2020-09-29 13:31 ` Kai-Heng Feng
2020-09-29 13:46 ` Neftin, Sasha
2020-09-29 15:08 ` Kai-Heng Feng
2020-09-29 15:11 ` David Laight
2020-09-29 15:12 ` Kai-Heng Feng
2020-09-30 6:54 ` Vitaly Lifshits
2020-10-05 6:23 ` Kai-Heng Feng
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