From: Zhen Lei <thunder.leizhen@huawei.com>
To: Wei Xu <xuwei5@hisilicon.com>, Rob Herring <robh+dt@kernel.org>,
"Jonathan Cameron" <Jonathan.Cameron@Huawei.com>,
devicetree <devicetree@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
linux-kernel <linux-kernel@vger.kernel.org>
Cc: Zhen Lei <thunder.leizhen@huawei.com>,
Libin <huawei.libin@huawei.com>,
Kefeng Wang <wangkefeng.wang@huawei.com>
Subject: [PATCH v6 17/17] dt-bindings: arm: hisilicon: convert LPC controller bindings to json-schema
Date: Wed, 30 Sep 2020 11:17:12 +0800 [thread overview]
Message-ID: <20200930031712.2365-18-thunder.leizhen@huawei.com> (raw)
In-Reply-To: <20200930031712.2365-1-thunder.leizhen@huawei.com>
Convert the Hisilicon Hip06 SoCs implement a Low Pin Count (LPC)
controller binding to DT schema format using json-schema.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
.../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ------------
.../bindings/arm/hisilicon/low-pin-count.yaml | 61 ++++++++++++++++++++++
2 files changed, 61 insertions(+), 33 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
deleted file mode 100644
index 10bd35f9207f2ee..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-Hisilicon Hip06 Low Pin Count device
- Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
- provides I/O access to some legacy ISA devices.
- Hip06 is based on arm64 architecture where there is no I/O space. So, the
- I/O ports here are not CPU addresses, and there is no 'ranges' property in
- LPC device node.
-
-Required properties:
-- compatible: value should be as follows:
- (a) "hisilicon,hip06-lpc"
- (b) "hisilicon,hip07-lpc"
-- #address-cells: must be 2 which stick to the ISA/EISA binding doc.
-- #size-cells: must be 1 which stick to the ISA/EISA binding doc.
-- reg: base memory range where the LPC register set is mapped.
-
-Note:
- The node name before '@' must be "isa" to represent the binding stick to the
- ISA/EISA binding specification.
-
-Example:
-
-isa@a01b0000 {
- compatible = "hisilicon,hip06-lpc";
- #address-cells = <2>;
- #size-cells = <1>;
- reg = <0x0 0xa01b0000 0x0 0x1000>;
-
- ipmi0: bt@e4 {
- compatible = "ipmi-bt";
- device_type = "ipmi";
- reg = <0x01 0xe4 0x04>;
- };
-};
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml b/Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml
new file mode 100644
index 000000000000000..3b36e683bb1511d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/low-pin-count.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon HiP06 Low Pin Count device
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+ Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which
+ provides I/O access to some legacy ISA devices.
+ HiP06 is based on arm64 architecture where there is no I/O space. So, the
+ I/O ports here are not CPU addresses, and there is no 'ranges' property in
+ LPC device node.
+
+properties:
+ $nodename:
+ pattern: '^isa@[0-9a-f]+$'
+ description: |
+ The node name before '@' must be "isa" to represent the binding stick
+ to the ISA/EISA binding specification.
+
+ compatible:
+ enum:
+ - hisilicon,hip06-lpc
+ - hisilicon,hip07-lpc
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 2
+
+ '#size-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties:
+ type: object
+
+examples:
+ - |
+ isa@a01b0000 {
+ compatible = "hisilicon,hip06-lpc";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <0xa01b0000 0x1000>;
+
+ ipmi0: bt@e4 {
+ compatible = "ipmi-bt";
+ device_type = "ipmi";
+ reg = <0x01 0xe4 0x04>;
+ };
+ };
+...
--
1.8.3
prev parent reply other threads:[~2020-09-30 3:19 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-30 3:16 [PATCH v6 00/17] add support for Hisilicon SD5203 SoC Zhen Lei
2020-09-30 3:16 ` [PATCH v6 01/17] dt-bindings: mfd: syscon: add some compatible strings for Hisilicon Zhen Lei
2020-09-30 7:11 ` Lee Jones
2020-09-30 7:21 ` Leizhen (ThunderTown)
2020-10-01 6:59 ` Lee Jones
2020-10-10 10:01 ` Leizhen (ThunderTown)
2020-10-01 6:27 ` Krzysztof Kozlowski
2020-09-30 3:16 ` [PATCH v6 02/17] dt-bindings: arm: hisilicon: delete the descriptions of HiP05/HiP06 controllers Zhen Lei
2020-10-01 6:28 ` Krzysztof Kozlowski
2020-09-30 3:16 ` [PATCH v6 03/17] dt-bindings: arm: hisilicon: split the dt-bindings of each controller into a separate file Zhen Lei
2020-10-01 6:32 ` Krzysztof Kozlowski
2020-09-30 3:16 ` [PATCH v6 04/17] dt-bindings: arm: hisilicon: convert Hisilicon board/soc bindings to json-schema Zhen Lei
2020-09-30 3:17 ` [PATCH v6 05/17] dt-bindings: arm: hisilicon: add binding for SD5203 SoC Zhen Lei
2020-09-30 3:17 ` [PATCH v6 06/17] ARM: hisi: add support " Zhen Lei
2020-09-30 3:17 ` [PATCH v6 07/17] ARM: debug: add UART early console support for SD5203 Zhen Lei
2020-09-30 3:17 ` [PATCH v6 08/17] ARM: dts: add SD5203 dts Zhen Lei
2020-10-01 6:36 ` Krzysztof Kozlowski
2020-09-30 3:17 ` [PATCH v6 09/17] ARM: dts: hisilicon: fix ststem controller compatible node Zhen Lei
2020-09-30 3:17 ` [PATCH v6 10/17] dt-bindings: arm: hisilicon: convert system controller bindings to json-schema Zhen Lei
2020-09-30 3:17 ` [PATCH v6 11/17] dt-bindings: arm: hisilicon: convert hisilicon,cpuctrl " Zhen Lei
2020-10-01 6:40 ` Krzysztof Kozlowski
2020-10-10 10:54 ` Leizhen (ThunderTown)
2020-09-30 3:17 ` [PATCH v6 12/17] dt-bindings: arm: hisilicon: convert hisilicon,pctrl " Zhen Lei
2020-09-30 3:17 ` [PATCH v6 13/17] dt-bindings: arm: hisilicon: convert hisilicon,hip04-fabric " Zhen Lei
2020-09-30 3:17 ` [PATCH v6 14/17] dt-bindings: arm: hisilicon: convert hisilicon,hip04-bootwrapper " Zhen Lei
2020-10-01 6:41 ` Krzysztof Kozlowski
2020-10-10 10:07 ` Leizhen (ThunderTown)
2020-09-30 3:17 ` [PATCH v6 15/17] dt-bindings: arm: hisilicon: convert Hi6220 domain controller " Zhen Lei
2020-10-06 19:04 ` Rob Herring
2020-09-30 3:17 ` [PATCH v6 16/17] dt-bindings: arm: hisilicon: convert hisilicon,hi3798cv200-perictrl " Zhen Lei
2020-10-01 6:35 ` Krzysztof Kozlowski
2020-10-10 10:56 ` Leizhen (ThunderTown)
2020-09-30 3:17 ` Zhen Lei [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200930031712.2365-18-thunder.leizhen@huawei.com \
--to=thunder.leizhen@huawei.com \
--cc=Jonathan.Cameron@Huawei.com \
--cc=devicetree@vger.kernel.org \
--cc=huawei.libin@huawei.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=wangkefeng.wang@huawei.com \
--cc=xuwei5@hisilicon.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).