From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
Will Deacon <will@kernel.org>
Cc: Evan Green <evgreen@chromium.org>, Tomasz Figa <tfiga@google.com>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<iommu@lists.linux-foundation.org>, <yong.wu@mediatek.com>,
<youlin.pei@mediatek.com>,
Nicolas Boichat <drinkcat@chromium.org>, <anan.sun@mediatek.com>,
<chao.hao@mediatek.com>, <ming-fan.chen@mediatek.com>,
Greg Kroah-Hartman <gregkh@google.com>, <kernel-team@android.com>
Subject: [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek
Date: Wed, 30 Sep 2020 15:06:34 +0800 [thread overview]
Message-ID: <20200930070647.10188-12-yong.wu@mediatek.com> (raw)
In-Reply-To: <20200930070647.10188-1-yong.wu@mediatek.com>
The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
(4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
34bit.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/io-pgtable-arm-v7s.c | 13 ++++++++++---
drivers/iommu/mtk_iommu.c | 2 +-
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
index 8362fdf76657..306bae2755ed 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -50,10 +50,17 @@
*/
#define ARM_V7S_ADDR_BITS 32
#define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4)
+/* MediaTek: totally 34bits, 14bits at lvl1 and 8bits at lvl2. */
+#define _ARM_V7S_LVL_BITS_MTK(lvl) (20 - (lvl) * 6)
#define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
#define ARM_V7S_TABLE_SHIFT 10
-#define ARM_V7S_PTES_PER_LVL(lvl, cfg) (1 << _ARM_V7S_LVL_BITS(lvl))
+#define ARM_V7S_PTES_PER_LVL(lvl, cfg) ({ \
+ int _lvl = lvl; \
+ !arm_v7s_is_mtk_enabled(cfg) ? \
+ (1 << _ARM_V7S_LVL_BITS(_lvl)) : (1 << _ARM_V7S_LVL_BITS_MTK(_lvl));\
+})
+
#define ARM_V7S_TABLE_SIZE(lvl, cfg) \
(ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte))
@@ -63,7 +70,7 @@
#define _ARM_V7S_IDX_MASK(lvl, cfg) (ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)
#define ARM_V7S_LVL_IDX(addr, lvl, cfg) ({ \
int _l = lvl; \
- ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
+ ((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
})
/*
@@ -755,7 +762,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
{
struct arm_v7s_io_pgtable *data;
- if (cfg->ias > ARM_V7S_ADDR_BITS)
+ if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
return NULL;
if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS))
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index f6a2e3eb59d2..6e85c9976a33 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -316,7 +316,7 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
IO_PGTABLE_QUIRK_TLBI_ON_MAP |
IO_PGTABLE_QUIRK_ARM_MTK_EXT,
.pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
- .ias = 32,
+ .ias = 34,
.oas = 35,
.tlb = &mtk_iommu_flush_ops,
.iommu_dev = data->dev,
--
2.18.0
next prev parent reply other threads:[~2020-09-30 7:09 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-30 7:06 [PATCH v3 00/24] MT8192 IOMMU support Yong Wu
2020-09-30 7:06 ` [PATCH v3 01/24] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema Yong Wu
2020-10-02 10:58 ` Krzysztof Kozlowski
2020-10-02 11:07 ` Krzysztof Kozlowski
2020-10-06 4:26 ` Yong Wu
2020-10-12 17:08 ` Krzysztof Kozlowski
2020-10-13 7:53 ` Yong Wu
2020-09-30 7:06 ` [PATCH v3 02/24] dt-bindings: memory: mediatek: Convert SMI " Yong Wu
2020-10-02 11:04 ` Krzysztof Kozlowski
2020-10-02 11:08 ` Krzysztof Kozlowski
2020-10-06 4:27 ` Yong Wu
2020-10-06 7:15 ` Krzysztof Kozlowski
2020-10-10 6:18 ` Yong Wu
2020-10-12 7:18 ` Krzysztof Kozlowski
2020-10-12 12:01 ` Yong Wu
2020-10-12 13:26 ` Krzysztof Kozlowski
2020-10-13 7:53 ` Yong Wu
2020-09-30 7:06 ` [PATCH v3 03/24] dt-bindings: memory: mediatek: Add a common larb-port header file Yong Wu
2020-09-30 7:06 ` [PATCH v3 04/24] dt-bindings: memory: mediatek: Extend LARB_NR_MAX to 32 Yong Wu
2020-09-30 7:06 ` [PATCH v3 05/24] dt-bindings: memory: mediatek: Add domain definition Yong Wu
2020-09-30 7:06 ` [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU Yong Wu
2020-10-02 11:10 ` Krzysztof Kozlowski
2020-10-06 4:26 ` Yong Wu
2020-10-06 7:19 ` Krzysztof Kozlowski
2020-09-30 7:06 ` [PATCH v3 07/24] iommu/mediatek: Use the common mtk-smi-larb-port.h Yong Wu
2020-09-30 7:06 ` [PATCH v3 08/24] iommu/io-pgtable-arm-v7s: Use ias to check the valid iova in unmap Yong Wu
2020-10-23 11:17 ` Will Deacon
2020-10-26 7:49 ` Yong Wu
2020-09-30 7:06 ` [PATCH v3 09/24] iommu/io-pgtable-arm-v7s: Extend PA34 for MediaTek Yong Wu
2020-10-23 11:22 ` Will Deacon
2020-09-30 7:06 ` [PATCH v3 10/24] iommu/io-pgtable-arm-v7s: Add cfg as a param in some macros Yong Wu
2020-10-23 11:23 ` Will Deacon
2020-09-30 7:06 ` Yong Wu [this message]
2020-10-23 11:21 ` [PATCH v3 11/24] iommu/io-pgtable-arm-v7s: Quad lvl1 pgtable for MediaTek Will Deacon
2020-10-26 7:45 ` Yong Wu
2020-10-23 14:10 ` Robin Murphy
2020-10-26 7:41 ` Yong Wu
2020-10-26 11:35 ` Robin Murphy
2020-09-30 7:06 ` [PATCH v3 12/24] iommu/mediatek: Move hw_init into attach_device Yong Wu
2020-09-30 7:06 ` [PATCH v3 13/24] iommu/mediatek: Add device link for smi-common and m4u Yong Wu
2020-09-30 7:06 ` [PATCH v3 14/24] iommu/mediatek: Add pm runtime callback Yong Wu
2020-09-30 7:06 ` [PATCH v3 15/24] iommu/mediatek: Add power-domain operation Yong Wu
2020-09-30 7:06 ` [PATCH v3 16/24] iommu/mediatek: Add iova reserved function Yong Wu
2020-09-30 7:06 ` [PATCH v3 17/24] iommu/mediatek: Add single domain Yong Wu
2020-09-30 7:06 ` [PATCH v3 18/24] iommu/mediatek: Support master use iova over 32bit Yong Wu
2020-10-06 7:18 ` Krzysztof Kozlowski
2020-09-30 7:06 ` [PATCH v3 19/24] iommu/mediatek: Support up to 34bit iova in tlb flush Yong Wu
2020-09-30 7:06 ` [PATCH v3 20/24] iommu/mediatek: Support report iova 34bit translation fault in ISR Yong Wu
2020-09-30 7:06 ` [PATCH v3 21/24] iommu/mediatek: Add support for multi domain Yong Wu
2020-09-30 7:06 ` [PATCH v3 22/24] iommu/mediatek: Adjust the structure Yong Wu
2020-09-30 7:06 ` [PATCH v3 23/24] iommu/mediatek: Add mt8192 support Yong Wu
2020-09-30 7:06 ` [PATCH v3 24/24] memory: mtk-smi: " Yong Wu
2020-10-02 11:15 ` Krzysztof Kozlowski
2020-10-26 20:08 ` [PATCH v3 00/24] MT8192 IOMMU support Krzysztof Kozlowski
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200930070647.10188-12-yong.wu@mediatek.com \
--to=yong.wu@mediatek.com \
--cc=anan.sun@mediatek.com \
--cc=chao.hao@mediatek.com \
--cc=devicetree@vger.kernel.org \
--cc=drinkcat@chromium.org \
--cc=evgreen@chromium.org \
--cc=gregkh@google.com \
--cc=iommu@lists.linux-foundation.org \
--cc=joro@8bytes.org \
--cc=kernel-team@android.com \
--cc=krzk@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=ming-fan.chen@mediatek.com \
--cc=robh+dt@kernel.org \
--cc=robin.murphy@arm.com \
--cc=srv_heupstream@mediatek.com \
--cc=tfiga@google.com \
--cc=will@kernel.org \
--cc=youlin.pei@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).