From: Sia Jee Heng <jee.heng.sia@intel.com>
To: vkoul@kernel.org, Eugeniy.Paltsev@synopsys.com
Cc: andriy.shevchenko@linux.intel.com, dmaengine@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 14/15] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers
Date: Mon, 12 Oct 2020 12:21:59 +0800 [thread overview]
Message-ID: <20201012042200.29787-15-jee.heng.sia@intel.com> (raw)
In-Reply-To: <20201012042200.29787-1-jee.heng.sia@intel.com>
Add support for Intel KeemBay AxiDMA BYTE and HALFWORD registers
programming.
Intel KeemBay AxiDMA supports data transfer between device to memory
and memory to device operations.
This code is needed by I2C, I3C, I2S, SPI and UART which uses FIFO
size of 8bits and 16bits to perform memory to device data transfer
operation. 0-padding functionality is provided to avoid
pre-processing of data on CPU.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 44 ++++++++++++++++---
1 file changed, 39 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 0f40b41fd5c0..d4fca3ffe67f 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -312,7 +312,7 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
struct axi_dma_desc *first)
{
u32 priority = chan->chip->dw->hdata->priority[chan->id];
- u32 reg, irq_mask;
+ u32 reg, irq_mask, reg_width, offset, val;
u8 lms = 0; /* Select AXI0 master for LLI fetching */
if (unlikely(axi_chan_is_hw_enable(chan))) {
@@ -334,6 +334,25 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
switch (chan->direction) {
case DMA_MEM_TO_DEV:
+ if (chan->chip->apb_regs) {
+ reg_width = __ffs(chan->config.dst_addr_width);
+ /*
+ * Configure Byte and Halfword register
+ * for MEM_TO_DEV only.
+ */
+ if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
+ offset = DMAC_APB_HALFWORD_WR_CH_EN;
+ val = ioread32(chan->chip->apb_regs + offset);
+ val |= BIT(chan->id);
+ iowrite32(val, chan->chip->apb_regs + offset);
+ } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
+ offset = DMAC_APB_BYTE_WR_CH_EN;
+ val = ioread32(chan->chip->apb_regs + offset);
+ val |= BIT(chan->id);
+ iowrite32(val, chan->chip->apb_regs + offset);
+ }
+ }
+
reg |= (chan->config.device_fc ?
DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
@@ -1054,8 +1073,9 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
{
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
u32 chan_active = BIT(chan->id) << DMAC_CHAN_EN_SHIFT;
+ u32 reg_width = __ffs(chan->config.dst_addr_width);
unsigned long flags;
- u32 val;
+ u32 offset, val;
int ret;
LIST_HEAD(head);
@@ -1067,9 +1087,23 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
dev_warn(dchan2dev(dchan),
"%s failed to stop\n", axi_chan_name(chan));
- if (chan->direction != DMA_MEM_TO_MEM)
- dw_axi_dma_set_hw_channel(chan->chip,
- chan->hw_hs_num, false);
+ if (chan->direction != DMA_MEM_TO_MEM) {
+ ret = dw_axi_dma_set_hw_channel(chan->chip,
+ chan->hw_hs_num, false);
+ if (ret == 0 && chan->direction == DMA_MEM_TO_DEV) {
+ if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
+ offset = DMAC_APB_BYTE_WR_CH_EN;
+ val = ioread32(chan->chip->apb_regs + offset);
+ val &= ~BIT(chan->id);
+ iowrite32(val, chan->chip->apb_regs + offset);
+ } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
+ offset = DMAC_APB_HALFWORD_WR_CH_EN;
+ val = ioread32(chan->chip->apb_regs + offset);
+ val &= ~BIT(chan->id);
+ iowrite32(val, chan->chip->apb_regs + offset);
+ }
+ }
+ }
spin_lock_irqsave(&chan->vc.lock, flags);
--
2.18.0
next prev parent reply other threads:[~2020-10-12 4:39 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-12 4:21 [PATCH 00/15] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
2020-10-12 4:21 ` [PATCH 01/15] dt-bindings: dma: Add YAML schemas for dw-axi-dmac Sia Jee Heng
2020-10-12 4:21 ` [PATCH 02/15] dmaengine: dw-axi-dmac: simplify descriptor management Sia Jee Heng
2020-10-12 4:21 ` [PATCH 03/15] dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources() Sia Jee Heng
2020-10-12 4:21 ` [PATCH 04/15] dmaengine: dw-axi-dmac: Add device_synchronize() callback Sia Jee Heng
2020-10-12 4:21 ` [PATCH 05/15] dmaengine: dw-axi-dmac: Add device_config operation Sia Jee Heng
2020-10-12 4:21 ` [PATCH 06/15] dmaengine: dw-axi-dmac: Support device_prep_slave_sg Sia Jee Heng
2020-10-12 4:21 ` [PATCH 07/15] dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic() Sia Jee Heng
2020-10-12 4:21 ` [PATCH 08/15] dmaengine: dw-axi-dmac: Support of_dma_controller_register() Sia Jee Heng
2020-10-12 4:21 ` [PATCH 09/15] dmaengine: dw-axi-dmac: Support burst residue granularity Sia Jee Heng
2020-10-12 4:21 ` [PATCH 10/15] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support Sia Jee Heng
2020-10-12 4:21 ` [PATCH 11/15] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA Sia Jee Heng
2020-10-12 4:21 ` [PATCH 12/15] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields Sia Jee Heng
2020-10-12 4:21 ` [PATCH 13/15] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake Sia Jee Heng
2020-10-12 4:21 ` Sia Jee Heng [this message]
2020-10-12 4:22 ` [PATCH 15/15] dmaengine: dw-axi-dmac: Set constraint to the Max segment size Sia Jee Heng
2020-10-12 13:59 ` [PATCH 00/15] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Andy Shevchenko
2020-10-13 5:49 ` Sia, Jee Heng
2020-10-13 7:01 ` Vinod Koul
2020-10-13 7:12 ` Sia, Jee Heng
2020-10-13 7:16 ` Vinod Koul
2020-10-16 14:51 ` Eugeniy Paltsev
2020-10-19 1:22 ` Sia, Jee Heng
2020-10-19 11:39 ` andriy.shevchenko
2020-10-21 1:54 ` Sia, Jee Heng
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