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From: "Ramuthevar,Vadivel MuruganX"  <vadivel.muruganx.ramuthevar@linux.intel.com>
To: vigneshr@ti.com, tudor.ambarus@microchip.com, broonie@kernel.org,
	linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
	robh+dt@kernel.org
Cc: devicetree@vger.kernel.org, miquel.raynal@bootlin.com,
	simon.k.r.goldschmidt@gmail.com, dinguyen@kernel.org,
	richard@nod.at, cheol.yong.kim@intel.com, qi-ming.wu@intel.com,
	Ramuthevar Vadivel Murugan 
	<vadivel.muruganx.ramuthevar@linux.intel.com>
Subject: [PATCH v2 1/6] spi: cadence-quadspi: Disable the DAC for Intel LGM SoC
Date: Wed, 21 Oct 2020 10:36:10 +0800	[thread overview]
Message-ID: <20201021023615.48982-2-vadivel.muruganx.ramuthevar@linux.intel.com> (raw)
In-Reply-To: <20201021023615.48982-1-vadivel.muruganx.ramuthevar@linux.intel.com>

From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>

On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use
Direct Access Controller(DAC).

This patch adds a quirk to disable the Direct Access Controller
for data transfer instead it uses indirect data transfer.

Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
---
 drivers/spi/spi-cadence-quadspi.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index d7b10c46fa70..3d017b484114 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1106,6 +1106,13 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
 	reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
 	writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
 
+	/* Disable direct access controller */
+	if (!cqspi->use_direct_mode) {
+		reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
+		reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
+		writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
+	}
+
 	cqspi_controller_enable(cqspi, 1);
 }
 
@@ -1388,6 +1395,10 @@ static const struct cqspi_driver_platdata am654_ospi = {
 	.quirks = CQSPI_NEEDS_WR_DELAY,
 };
 
+static const struct cqspi_driver_platdata intel_lgm_qspi = {
+	.quirks = CQSPI_DISABLE_DAC_MODE,
+};
+
 static const struct of_device_id cqspi_dt_ids[] = {
 	{
 		.compatible = "cdns,qspi-nor",
@@ -1403,6 +1414,7 @@ static const struct of_device_id cqspi_dt_ids[] = {
 	},
 	{
 		.compatible = "intel,lgm-qspi",
+		.data = &intel_lgm_qspi,
 	},
 	{ /* end of table */ }
 };
-- 
2.11.0


  reply	other threads:[~2020-10-21  2:36 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-21  2:36 [PATCH v2 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-10-21  2:36 ` Ramuthevar,Vadivel MuruganX [this message]
2020-10-21  2:36 ` [PATCH v2 2/6] spi: cadence-quadspi: Add multi-chipselect " Ramuthevar,Vadivel MuruganX
2020-10-21  2:36 ` [PATCH v2 3/6] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi Ramuthevar,Vadivel MuruganX
2020-10-21  2:36 ` [PATCH v2 4/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml Ramuthevar,Vadivel MuruganX
2020-10-21  2:36 ` [PATCH v2 5/6] dt-bindings: spi: Add compatible for Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-10-21  2:36 ` [PATCH v2 6/6] " Ramuthevar,Vadivel MuruganX

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