[1/2] clk: imx: composite-8m: Add DRAM clock registration variant
diff mbox series

Message ID 1603284043-27059-2-git-send-email-abel.vesa@nxp.com
State New, archived
Headers show
Series
  • clk: imx: Make the dram_apb and dram_alt as read-only
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Commit Message

Abel Vesa Oct. 21, 2020, 12:40 p.m. UTC
The switch between parents for dram_apb and dram_alt is done in EL3,
so lets mark the mux and divider as read only with the CLK_DIVIDER_READ_ONLY
and CLK_MUX_READ_ONLY flags.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 drivers/clk/imx/clk-composite-8m.c | 7 +++++++
 drivers/clk/imx/clk.h              | 6 ++++++
 2 files changed, 13 insertions(+)

Patch
diff mbox series

diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 2c309e3..c3231eb 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -211,6 +211,13 @@  struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 		div->width = PCG_PREDIV_WIDTH;
 		divider_ops = &imx8m_clk_composite_divider_ops;
 		mux_ops = &imx8m_clk_composite_mux_ops;
+	} else if (composite_flags & IMX_COMPOSITE_DRAM) {
+		div->shift = PCG_PREDIV_SHIFT;
+		div->width = PCG_PREDIV_WIDTH;
+		div->flags = CLK_DIVIDER_READ_ONLY;
+		mux->flags = CLK_MUX_READ_ONLY;
+		divider_ops = &clk_divider_ops;
+		mux_ops = &clk_mux_ops;
 	} else {
 		div->shift = PCG_PREDIV_SHIFT;
 		div->width = PCG_PREDIV_WIDTH;
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 3b796b3..70c57d2 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -535,6 +535,7 @@  struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
 
 #define IMX_COMPOSITE_CORE	BIT(0)
 #define IMX_COMPOSITE_BUS	BIT(1)
+#define IMX_COMPOSITE_DRAM	BIT(2)
 
 struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 					    const char * const *parent_names,
@@ -565,6 +566,11 @@  struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
 		ARRAY_SIZE(parent_names), reg, 0, \
 		flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
 
+#define __imx8m_clk_hw_composite_dram(name, parent_names, reg, flags) \
+	imx8m_clk_hw_composite_flags(name, parent_names, \
+		ARRAY_SIZE(parent_names), reg, IMX_COMPOSITE_DRAM, \
+		flags | CLK_GET_RATE_NOCACHE | CLK_OPS_PARENT_ENABLE)
+
 #define __imx8m_clk_composite(name, parent_names, reg, flags) \
 	to_clk(__imx8m_clk_hw_composite(name, parent_names, reg, flags))