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From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Nicolas Boichat <drinkcat@chromium.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
	<srv_heupstream@mediatek.com>, Weiyi Lu <weiyi.lu@mediatek.com>
Subject: [PATCH 08/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT8135
Date: Thu, 22 Oct 2020 20:56:01 +0800	[thread overview]
Message-ID: <1603371365-30863-9-git-send-email-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <1603371365-30863-1-git-send-email-weiyi.lu@mediatek.com>

remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
 drivers/clk/mediatek/clk-mt8135.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c
index 9b4b645..a1d462f 100644
--- a/drivers/clk/mediatek/clk-mt8135.c
+++ b/drivers/clk/mediatek/clk-mt8135.c
@@ -611,16 +611,16 @@ static void __init mtk_pericfg_init(struct device_node *node)
 	}
 
 static const struct mtk_pll_data plls[] = {
-	PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
-	PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000001, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
-	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000001, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0),
-	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000001, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000001, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0),
-	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000001, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
-	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000001, 0, 31, 0x294, 6, 0x0, 0x298, 0),
-	PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8,	0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
-	PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000001, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
-	PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c,	0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
+	PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x204, 24, 0x0, 0x204, 0),
+	PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
+	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0),
+	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9),
+	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0),
+	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
+	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294, 6, 0x0, 0x298, 0),
+	PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
+	PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
+	PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
 };
 
 static void __init mtk_apmixedsys_init(struct device_node *node)
-- 
1.8.1.1.dirty

  parent reply	other threads:[~2020-10-22 12:56 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-22 12:55 [PATCH 00/12] Clean up the pll_en_bit from en_mask on all the MediaTek clock drivers Weiyi Lu
2020-10-22 12:55 ` [PATCH 01/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT2701 Weiyi Lu
2020-10-22 12:55 ` [PATCH 02/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT2712 Weiyi Lu
2020-10-22 12:55 ` [PATCH 03/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT6765 Weiyi Lu
2020-10-22 12:55 ` [PATCH 04/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT6779 Weiyi Lu
2020-10-22 12:55 ` [PATCH 05/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT6797 Weiyi Lu
2020-10-22 12:55 ` [PATCH 06/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT7622 Weiyi Lu
2020-10-22 12:56 ` [PATCH 07/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT7629 Weiyi Lu
2020-10-22 12:56 ` Weiyi Lu [this message]
2020-10-22 12:56 ` [PATCH 09/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT8173 Weiyi Lu
2020-10-22 12:56 ` [PATCH 10/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT8183 Weiyi Lu
2020-10-28 10:27   ` Fabien Parent
2020-11-09  2:22     ` Weiyi Lu
2020-10-22 12:56 ` [PATCH 11/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT8516 Weiyi Lu
2020-10-22 12:56 ` [PATCH 12/12] clk: mediatek: limit en_mask to a pure div_en_mask Weiyi Lu

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