From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Stephen Boyd <sboyd@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
<srv_heupstream@mediatek.com>, Weiyi Lu <weiyi.lu@mediatek.com>
Subject: [PATCH 01/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT2701
Date: Thu, 22 Oct 2020 20:55:54 +0800 [thread overview]
Message-ID: <1603371365-30863-2-git-send-email-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <1603371365-30863-1-git-send-email-weiyi.lu@mediatek.com>
remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
that only used for pll dividers.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/clk/mediatek/clk-mt2701.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 695be0f..462a998 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -934,31 +934,31 @@ static int mtk_pericfg_init(struct platform_device *pdev)
}
static const struct mtk_pll_data apmixed_plls[] = {
- PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000001,
+ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000000,
PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0),
- PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000001,
+ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000000,
HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0),
- PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000001,
+ PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000000,
HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14),
- PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0,
+ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0, 0,
21, 0x230, 4, 0x0, 0x234, 0),
- PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
+ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0, 0,
21, 0x240, 4, 0x0, 0x244, 0),
- PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
+ PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0, 0,
21, 0x250, 4, 0x0, 0x254, 0),
- PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
+ PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0, 0,
31, 0x270, 4, 0x0, 0x274, 0),
- PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
+ PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0, 0,
31, 0x280, 4, 0x0, 0x284, 0),
- PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
+ PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0, 0,
31, 0x290, 4, 0x0, 0x294, 0),
- PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0,
+ PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0, 0,
31, 0x2a0, 4, 0x0, 0x2a4, 0),
- PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0,
+ PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0, 0,
31, 0x2b0, 4, 0x0, 0x2b4, 0),
- PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0,
+ PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0, 0,
31, 0x2c0, 4, 0x0, 0x2c4, 0),
- PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0,
+ PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0, 0,
21, 0x2d0, 4, 0x0, 0x2d4, 0),
};
--
1.8.1.1.dirty
next prev parent reply other threads:[~2020-10-22 12:56 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-22 12:55 [PATCH 00/12] Clean up the pll_en_bit from en_mask on all the MediaTek clock drivers Weiyi Lu
2020-10-22 12:55 ` Weiyi Lu [this message]
2020-10-22 12:55 ` [PATCH 02/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT2712 Weiyi Lu
2020-10-22 12:55 ` [PATCH 03/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT6765 Weiyi Lu
2020-10-22 12:55 ` [PATCH 04/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT6779 Weiyi Lu
2020-10-22 12:55 ` [PATCH 05/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT6797 Weiyi Lu
2020-10-22 12:55 ` [PATCH 06/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT7622 Weiyi Lu
2020-10-22 12:56 ` [PATCH 07/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT7629 Weiyi Lu
2020-10-22 12:56 ` [PATCH 08/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT8135 Weiyi Lu
2020-10-22 12:56 ` [PATCH 09/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT8173 Weiyi Lu
2020-10-22 12:56 ` [PATCH 10/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT8183 Weiyi Lu
2020-10-28 10:27 ` Fabien Parent
2020-11-09 2:22 ` Weiyi Lu
2020-10-22 12:56 ` [PATCH 11/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT8516 Weiyi Lu
2020-10-22 12:56 ` [PATCH 12/12] clk: mediatek: limit en_mask to a pure div_en_mask Weiyi Lu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1603371365-30863-2-git-send-email-weiyi.lu@mediatek.com \
--to=weiyi.lu@mediatek.com \
--cc=drinkcat@chromium.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=sboyd@kernel.org \
--cc=srv_heupstream@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).