From: guoren@kernel.org
To: palmerdabbelt@google.com, paul.walmsley@sifive.com,
anup@brainfault.org, greentime.hu@sifive.com, zong.li@sifive.com,
atish.patra@wdc.com, tglx@linutronix.de, jason@lakedaemon.net,
maz@kernel.org, wesley@sifive.com, yash.shah@sifive.com,
hch@lst.de
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
guoren@kernel.org, Guo Ren <guoren@linux.alibaba.com>
Subject: [PATCH 1/3] irqchip/irq-sifive-plic: Fixup wrong size of xxx_PER_HART and reg base
Date: Fri, 23 Oct 2020 10:17:23 +0000 [thread overview]
Message-ID: <1603448245-79429-1-git-send-email-guoren@kernel.org> (raw)
From: Guo Ren <guoren@linux.alibaba.com>
ENABLE and CONTEXT registers contain M & S status for per-hart, so
ref to the specification the correct definition is double to the
current value.
The value of hart_base and enable_base should be calculated by real
physical hartid not software id. Sometimes the CPU node's <reg>
from dts is not equal to the sequence index.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
---
drivers/irqchip/irq-sifive-plic.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index eaa3e9f..2e56576 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -44,16 +44,16 @@
* Each hart context has a vector of interrupt enable bits associated with it.
* There's one bit for each interrupt source.
*/
-#define ENABLE_BASE 0x2000
-#define ENABLE_PER_HART 0x80
+#define ENABLE_BASE 0x2080
+#define ENABLE_PER_HART 0x100
/*
* Each hart context has a set of control registers associated with it. Right
* now there's only two: a source priority threshold over which the hart will
* take an interrupt, and a register to claim interrupts.
*/
-#define CONTEXT_BASE 0x200000
-#define CONTEXT_PER_HART 0x1000
+#define CONTEXT_BASE 0x201000
+#define CONTEXT_PER_HART 0x2000
#define CONTEXT_THRESHOLD 0x00
#define CONTEXT_CLAIM 0x04
@@ -358,10 +358,10 @@ static int __init plic_init(struct device_node *node,
cpumask_set_cpu(cpu, &priv->lmask);
handler->present = true;
handler->hart_base =
- priv->regs + CONTEXT_BASE + i * CONTEXT_PER_HART;
+ priv->regs + CONTEXT_BASE + hartid * CONTEXT_PER_HART;
raw_spin_lock_init(&handler->enable_lock);
handler->enable_base =
- priv->regs + ENABLE_BASE + i * ENABLE_PER_HART;
+ priv->regs + ENABLE_BASE + hartid * ENABLE_PER_HART;
handler->priv = priv;
done:
for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
--
2.7.4
next reply other threads:[~2020-10-23 10:18 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-23 10:17 guoren [this message]
2020-10-23 10:17 ` [PATCH 2/3] irqchip/irq-sifive-plic: Fixup couldn't broadcast to multi CPUs guoren
2020-10-23 11:27 ` Anup Patel
2020-10-24 3:38 ` Guo Ren
2020-10-23 10:17 ` [PATCH 3/3] irqchip/irq-sifive-plic: Fixup set_affinity enable irq unexpected guoren
2020-10-23 11:33 ` Anup Patel
2020-10-23 11:42 ` [PATCH 1/3] irqchip/irq-sifive-plic: Fixup wrong size of xxx_PER_HART and reg base Anup Patel
2020-10-24 3:09 ` Guo Ren
2020-10-25 9:17 ` Anup Patel
2020-10-26 15:01 ` Guo Ren
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