From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Georgi Djakov <georgi.djakov@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
MyungJoo Ham <myungjoo.ham@samsung.com>,
Kyungmin Park <kyungmin.park@samsung.com>,
Chanwoo Choi <cw00.choi@samsung.com>,
Mikko Perttunen <cyndis@kapsi.fi>,
Viresh Kumar <vireshk@kernel.org>,
Peter Geis <pgwipeout@gmail.com>,
Nicolas Chauvet <kwizart@gmail.com>,
Krzysztof Kozlowski <krzk@kernel.org>
Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
devicetree@vger.kernel.org
Subject: [PATCH v6 42/52] memory: tegra124: Support interconnect framework
Date: Mon, 26 Oct 2020 01:17:25 +0300 [thread overview]
Message-ID: <20201025221735.3062-43-digetx@gmail.com> (raw)
In-Reply-To: <20201025221735.3062-1-digetx@gmail.com>
Now Internal and External memory controllers are memory interconnection
providers. This allows us to use interconnect API for tuning of memory
configuration. EMC driver now supports OPPs and DVFS.
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/memory/tegra/Kconfig | 1 +
drivers/memory/tegra/tegra124-emc.c | 186 +++++++++++++++++++++++++++-
drivers/memory/tegra/tegra124.c | 31 +++++
3 files changed, 216 insertions(+), 2 deletions(-)
diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig
index 94536dc4c495..3d1ef3ec1a2d 100644
--- a/drivers/memory/tegra/Kconfig
+++ b/drivers/memory/tegra/Kconfig
@@ -34,6 +34,7 @@ config TEGRA124_EMC
tristate "NVIDIA Tegra124 External Memory Controller driver"
default y
depends on TEGRA_MC && ARCH_TEGRA_124_SOC
+ select PM_OPP
help
This driver is for the External Memory Controller (EMC) found on
Tegra124 chips. The EMC controls the external DRAM on the board.
diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c
index 2814b1b4a1d9..bdce7bebe0ef 100644
--- a/drivers/memory/tegra/tegra124-emc.c
+++ b/drivers/memory/tegra/tegra124-emc.c
@@ -12,17 +12,21 @@
#include <linux/clk/tegra.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
+#include <linux/interconnect-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
#include <linux/sort.h>
#include <linux/string.h>
#include <soc/tegra/fuse.h>
#include <soc/tegra/mc.h>
+#include "mc.h"
+
#define EMC_FBIO_CFG5 0x104
#define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
#define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
@@ -482,6 +486,9 @@ struct tegra_emc {
unsigned long min_rate;
unsigned long max_rate;
} debugfs;
+
+ struct opp_table *opp_table;
+ struct icc_provider provider;
};
/* Timing change sequence functions */
@@ -1177,6 +1184,169 @@ static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc)
emc, &tegra_emc_debug_max_rate_fops);
}
+static inline struct tegra_emc *
+to_tegra_emc_provider(struct icc_provider *provider)
+{
+ return container_of(provider, struct tegra_emc, provider);
+}
+
+static struct icc_node_data *
+emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
+{
+ struct icc_provider *provider = data;
+ struct icc_node_data *ndata;
+ struct icc_node *node;
+
+ /* External Memory is the only possible ICC route */
+ list_for_each_entry(node, &provider->nodes, node_list) {
+ if (node->id != TEGRA_ICC_EMEM)
+ continue;
+
+ ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
+ if (!ndata)
+ return ERR_PTR(-ENOMEM);
+
+ /*
+ * SRC and DST nodes should have matching TAG in order to have
+ * it set by default for a requested path.
+ */
+ ndata->tag = TEGRA_MC_ICC_TAG_ISO;
+ ndata->node = node;
+
+ return ndata;
+ }
+
+ return ERR_PTR(-EINVAL);
+}
+
+static int emc_icc_set(struct icc_node *src, struct icc_node *dst)
+{
+ struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);
+ unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw);
+ unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw);
+ unsigned long long rate = max(avg_bw, peak_bw);
+ unsigned int dram_data_bus_width_bytes = 8;
+ unsigned int ddr = 2;
+ int err;
+
+ /*
+ * Tegra124 EMC runs on a clock rate of SDRAM bus. This means that
+ * EMC clock rate is twice smaller than the peak data rate because
+ * data is sample on both EMC clock edges.
+ */
+ do_div(rate, ddr * dram_data_bus_width_bytes);
+ rate = min_t(u64, rate, U32_MAX);
+
+ err = dev_pm_opp_set_rate(emc->dev, rate);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static int tegra_emc_interconnect_init(struct tegra_emc *emc)
+{
+ const struct tegra_mc_soc *soc = emc->mc->soc;
+ struct icc_node *node;
+ int err;
+
+ emc->provider.dev = emc->dev;
+ emc->provider.set = emc_icc_set;
+ emc->provider.data = &emc->provider;
+ emc->provider.aggregate = soc->icc_ops->aggregate;
+ emc->provider.xlate_extended = emc_of_icc_xlate_extended;
+
+ err = icc_provider_add(&emc->provider);
+ if (err)
+ goto err_msg;
+
+ /* create External Memory Controller node */
+ node = icc_node_create(TEGRA_ICC_EMC);
+ err = PTR_ERR_OR_ZERO(node);
+ if (err)
+ goto del_provider;
+
+ node->name = "External Memory Controller";
+ icc_node_add(node, &emc->provider);
+
+ /* link External Memory Controller to External Memory (DRAM) */
+ err = icc_link_create(node, TEGRA_ICC_EMEM);
+ if (err)
+ goto remove_nodes;
+
+ /* create External Memory node */
+ node = icc_node_create(TEGRA_ICC_EMEM);
+ err = PTR_ERR_OR_ZERO(node);
+ if (err)
+ goto remove_nodes;
+
+ node->name = "External Memory (DRAM)";
+ icc_node_add(node, &emc->provider);
+
+ return 0;
+
+remove_nodes:
+ icc_nodes_remove(&emc->provider);
+del_provider:
+ icc_provider_del(&emc->provider);
+err_msg:
+ dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
+
+ return err;
+}
+
+static int tegra_emc_opp_table_init(struct tegra_emc *emc)
+{
+ u32 hw_version = BIT(tegra_sku_info.soc_speedo_id);
+ struct opp_table *opp_table;
+ const char *rname = "core";
+ int err;
+
+ /*
+ * Legacy device-trees don't have OPP table and EMC driver isn't
+ * useful in this case.
+ */
+ if (!device_property_present(emc->dev, "operating-points-v2")) {
+ dev_err(emc->dev, "OPP table not found\n");
+ dev_err(emc->dev, "please update your device tree\n");
+ return -ENODEV;
+ }
+
+ /* voltage scaling is optional */
+ if (device_property_present(emc->dev, "core-supply"))
+ emc->opp_table = dev_pm_opp_set_regulators(emc->dev, &rname, 1);
+ else
+ emc->opp_table = dev_pm_opp_get_opp_table(emc->dev);
+
+ if (IS_ERR(emc->opp_table))
+ return dev_err_probe(emc->dev, PTR_ERR(emc->opp_table),
+ "failed to prepare OPP table\n");
+
+ opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1);
+ err = PTR_ERR_OR_ZERO(opp_table);
+ if (err) {
+ dev_err(emc->dev, "failed to set supported HW: %d\n", err);
+ goto put_table;
+ }
+
+ err = dev_pm_opp_of_add_table(emc->dev);
+ if (err) {
+ dev_err(emc->dev, "failed to add OPP table: %d\n", err);
+ goto put_hw;
+ }
+
+ dev_info(emc->dev, "OPP HW ver. 0x%x\n", hw_version);
+
+ return 0;
+
+put_hw:
+ dev_pm_opp_put_supported_hw(emc->opp_table);
+put_table:
+ dev_pm_opp_put_opp_table(emc->opp_table);
+
+ return err;
+}
+
static int tegra_emc_probe(struct platform_device *pdev)
{
struct device_node *np;
@@ -1226,14 +1396,20 @@ static int tegra_emc_probe(struct platform_device *pdev)
return err;
}
- platform_set_drvdata(pdev, emc);
-
tegra124_clk_set_emc_callbacks(tegra_emc_prepare_timing_change,
tegra_emc_complete_timing_change);
+ platform_set_drvdata(pdev, emc);
+
+ err = tegra_emc_opp_table_init(emc);
+ if (err)
+ goto unset_cb;
+
if (IS_ENABLED(CONFIG_DEBUG_FS))
emc_debugfs_init(&pdev->dev, emc);
+ tegra_emc_interconnect_init(emc);
+
/*
* Don't allow the kernel module to be unloaded. Unloading adds some
* extra complexity which doesn't really worth the effort in a case of
@@ -1242,6 +1418,11 @@ static int tegra_emc_probe(struct platform_device *pdev)
try_module_get(THIS_MODULE);
return 0;
+
+unset_cb:
+ tegra124_clk_set_emc_callbacks(NULL, NULL);
+
+ return err;
};
static struct platform_driver tegra_emc_driver = {
@@ -1250,6 +1431,7 @@ static struct platform_driver tegra_emc_driver = {
.name = "tegra-emc",
.of_match_table = tegra_emc_of_match,
.suppress_bind_attrs = true,
+ .sync_state = icc_sync_state,
},
};
module_platform_driver(tegra_emc_driver);
diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c
index e2389573d3c0..b69d76cd0411 100644
--- a/drivers/memory/tegra/tegra124.c
+++ b/drivers/memory/tegra/tegra124.c
@@ -1010,6 +1010,35 @@ static const struct tegra_mc_reset tegra124_mc_resets[] = {
TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2),
};
+static int tegra124_mc_icc_set(struct icc_node *src, struct icc_node *dst)
+{
+ /* TODO: program PTSA */
+ return 0;
+}
+
+static int tegra124_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw,
+ u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
+{
+ /*
+ * ISO clients need to reserve extra bandwidth up-front because
+ * there could high bandwidth pressure during initial fulling-up
+ * of the client's FIFO buffers. Secondly, we need to take into
+ * account impurities of the memory subsystem.
+ */
+ if (tag == TEGRA_MC_ICC_TAG_ISO)
+ peak_bw = tegra_mc_scale_percents(peak_bw, 400);
+
+ *agg_avg += avg_bw;
+ *agg_peak = max(*agg_peak, peak_bw);
+
+ return 0;
+}
+
+static const struct tegra_mc_icc_ops tegra124_mc_icc_ops = {
+ .aggregate = tegra124_mc_icc_aggreate,
+ .set = tegra124_mc_icc_set,
+};
+
#ifdef CONFIG_ARCH_TEGRA_124_SOC
static const unsigned long tegra124_mc_emem_regs[] = {
MC_EMEM_ARB_CFG,
@@ -1061,6 +1090,7 @@ const struct tegra_mc_soc tegra124_mc_soc = {
.reset_ops = &tegra_mc_reset_ops_common,
.resets = tegra124_mc_resets,
.num_resets = ARRAY_SIZE(tegra124_mc_resets),
+ .icc_ops = &tegra124_mc_icc_ops,
};
#endif /* CONFIG_ARCH_TEGRA_124_SOC */
@@ -1091,5 +1121,6 @@ const struct tegra_mc_soc tegra132_mc_soc = {
.reset_ops = &tegra_mc_reset_ops_common,
.resets = tegra124_mc_resets,
.num_resets = ARRAY_SIZE(tegra124_mc_resets),
+ .icc_ops = &tegra124_mc_icc_ops,
};
#endif /* CONFIG_ARCH_TEGRA_132_SOC */
--
2.27.0
next prev parent reply other threads:[~2020-10-25 22:19 UTC|newest]
Thread overview: 143+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-25 22:16 [PATCH v6 00/52] Introduce memory interconnect for NVIDIA Tegra SoCs Dmitry Osipenko
2020-10-25 22:16 ` [PATCH v6 01/52] clk: tegra: Export Tegra20 EMC kernel symbols Dmitry Osipenko
2020-10-27 13:04 ` Thierry Reding
2020-10-25 22:16 ` [PATCH v6 02/52] soc/tegra: fuse: Export tegra_read_ram_code() Dmitry Osipenko
2020-10-27 13:17 ` Thierry Reding
2020-10-25 22:16 ` [PATCH v6 03/52] dt-bindings: memory: tegra20: emc: Correct registers range in example Dmitry Osipenko
2020-10-27 13:18 ` Thierry Reding
2020-10-28 15:16 ` Rob Herring
2020-10-25 22:16 ` [PATCH v6 04/52] dt-bindings: memory: tegra20: emc: Document nvidia,memory-controller property Dmitry Osipenko
2020-10-27 8:54 ` Krzysztof Kozlowski
2020-10-27 19:17 ` Dmitry Osipenko
2020-10-27 19:30 ` Krzysztof Kozlowski
2020-10-27 20:37 ` Dmitry Osipenko
2020-10-28 15:23 ` Rob Herring
2020-10-28 15:35 ` Krzysztof Kozlowski
2020-10-28 15:23 ` [PATCH v6 04/52] dt-bindings: memory: tegra20: emc: Document nvidia, memory-controller property Rob Herring
2020-10-25 22:16 ` [PATCH v6 05/52] dt-bindings: memory: tegra20: mc: Document new interconnect property Dmitry Osipenko
2020-10-27 8:55 ` Krzysztof Kozlowski
2020-10-27 19:17 ` Dmitry Osipenko
2020-10-27 19:34 ` Krzysztof Kozlowski
2020-10-25 22:16 ` [PATCH v6 06/52] dt-bindings: memory: tegra20: emc: " Dmitry Osipenko
2020-10-27 9:03 ` Krzysztof Kozlowski
2020-10-25 22:16 ` [PATCH v6 07/52] dt-bindings: memory: tegra20: emc: Document OPP table and voltage regulator Dmitry Osipenko
2020-10-27 8:57 ` Krzysztof Kozlowski
2020-10-25 22:16 ` [PATCH v6 08/52] dt-bindings: memory: tegra20: emc: Document mfd-simple compatible and statistics sub-device Dmitry Osipenko
2020-10-27 9:02 ` Krzysztof Kozlowski
2020-10-27 19:22 ` Dmitry Osipenko
2020-10-27 19:44 ` Krzysztof Kozlowski
2020-10-27 20:18 ` Dmitry Osipenko
2020-10-28 15:26 ` Rob Herring
2020-10-31 19:53 ` Dmitry Osipenko
2020-10-27 13:22 ` Thierry Reding
2020-10-27 19:23 ` Dmitry Osipenko
2020-10-28 15:28 ` Rob Herring
2020-10-25 22:16 ` [PATCH v6 09/52] dt-bindings: memory: tegra30: mc: Document new interconnect property Dmitry Osipenko
2020-10-27 9:05 ` Krzysztof Kozlowski
2020-10-27 19:18 ` Dmitry Osipenko
2020-10-27 19:39 ` Krzysztof Kozlowski
2020-10-25 22:16 ` [PATCH v6 10/52] dt-bindings: memory: tegra30: emc: " Dmitry Osipenko
2020-10-25 22:16 ` [PATCH v6 11/52] dt-bindings: memory: tegra30: emc: Document OPP table and voltage regulator Dmitry Osipenko
2020-10-28 15:29 ` Rob Herring
2020-10-25 22:16 ` [PATCH v6 12/52] dt-bindings: memory: tegra124: mc: Document new interconnect property Dmitry Osipenko
2020-10-26 12:49 ` Rob Herring
2020-10-25 22:16 ` [PATCH v6 13/52] dt-bindings: memory: tegra124: emc: " Dmitry Osipenko
2020-10-26 12:51 ` Rob Herring
2020-10-27 10:25 ` Krzysztof Kozlowski
2020-10-27 19:19 ` Dmitry Osipenko
2020-10-27 19:48 ` Krzysztof Kozlowski
2020-10-27 20:16 ` Dmitry Osipenko
2020-10-28 19:27 ` Krzysztof Kozlowski
2020-10-25 22:16 ` [PATCH v6 14/52] dt-bindings: memory: tegra124: emc: Document OPP table and voltage regulator Dmitry Osipenko
2020-10-28 15:30 ` Rob Herring
2020-10-25 22:16 ` [PATCH v6 15/52] dt-bindings: tegra30-actmon: Document OPP and interconnect properties Dmitry Osipenko
2020-10-28 15:30 ` Rob Herring
2020-10-25 22:16 ` [PATCH v6 16/52] dt-bindings: host1x: Document new " Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 17/52] dt-bindings: memory: tegra20: Add memory client IDs Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 18/52] dt-bindings: memory: tegra30: " Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 19/52] dt-bindings: memory: tegra124: " Dmitry Osipenko
2020-10-28 15:31 ` Rob Herring
2020-10-25 22:17 ` [PATCH v6 20/52] ARM: tegra: Correct EMC registers size in Tegra20 device-tree Dmitry Osipenko
2020-10-27 9:10 ` Krzysztof Kozlowski
2020-10-27 20:43 ` Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 21/52] ARM: tegra: Add interconnect properties to " Dmitry Osipenko
2020-10-27 9:12 ` Krzysztof Kozlowski
2020-10-27 13:30 ` Thierry Reding
2020-10-25 22:17 ` [PATCH v6 22/52] ARM: tegra: Add interconnect properties to Tegra30 device-tree Dmitry Osipenko
2020-10-27 9:15 ` Krzysztof Kozlowski
2020-10-27 19:23 ` Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 23/52] ARM: tegra: Add interconnect properties to Tegra124 device-tree Dmitry Osipenko
2020-10-27 9:16 ` Krzysztof Kozlowski
2020-10-25 22:17 ` [PATCH v6 24/52] ARM: tegra: Add nvidia,memory-controller phandle to Tegra20 EMC device-tree Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 25/52] ARM: tegra: Add DVFS properties to Tegra20 EMC device-tree node Dmitry Osipenko
2020-10-27 9:18 ` Krzysztof Kozlowski
2020-10-25 22:17 ` [PATCH v6 26/52] ARM: tegra: Add DVFS properties to Tegra30 EMC and ACTMON device-tree nodes Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 27/52] ARM: tegra: Add DVFS properties to Tegra124 " Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 28/52] memory: tegra: Add and use devm_tegra_get_memory_controller() Dmitry Osipenko
2020-10-27 9:42 ` Krzysztof Kozlowski
2020-10-27 19:24 ` Dmitry Osipenko
2020-10-27 13:35 ` Thierry Reding
2020-10-25 22:17 ` [PATCH v6 29/52] memory: tegra-mc: Add interconnect framework Dmitry Osipenko
2020-10-27 13:48 ` Thierry Reding
2020-10-27 19:30 ` Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 30/52] memory: tegra20-emc: Make driver modular Dmitry Osipenko
2020-10-27 13:49 ` Thierry Reding
2020-10-25 22:17 ` [PATCH v6 31/52] memory: tegra20-emc: Use devm_platform_ioremap_resource() Dmitry Osipenko
2020-10-27 13:50 ` Thierry Reding
2020-10-27 13:57 ` Krzysztof Kozlowski
2020-10-25 22:17 ` [PATCH v6 32/52] memory: tegra20-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko
2020-10-27 13:52 ` Thierry Reding
2020-10-27 19:38 ` Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 33/52] memory: tegra20: Support interconnect framework Dmitry Osipenko
2020-10-27 10:09 ` Krzysztof Kozlowski
2020-10-27 20:25 ` Dmitry Osipenko
2020-10-27 14:11 ` Thierry Reding
2020-10-27 20:22 ` Dmitry Osipenko
2020-10-27 21:12 ` Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 34/52] memory: tegra20-emc: Don't parse emc-stats node Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 35/52] memory: tegra: Add missing latency allowness entry for Page Table Cache Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 36/52] memory: tegra: Add FIFO sizes to Tegra30 memory clients Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 37/52] memory: tegra30-emc: Make driver modular Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 38/52] memory: tegra30-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 39/52] memory: tegra30: Support interconnect framework Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 40/52] memory: tegra124-emc: Make driver modular Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 41/52] memory: tegra124-emc: Use devm_platform_ioremap_resource() Dmitry Osipenko
2020-10-27 10:27 ` Krzysztof Kozlowski
2020-10-27 20:30 ` Dmitry Osipenko
2020-10-28 19:28 ` Krzysztof Kozlowski
2020-10-25 22:17 ` Dmitry Osipenko [this message]
2020-10-25 22:17 ` [PATCH v6 43/52] memory: tegra: Remove superfluous error messages around platform_get_irq() Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 44/52] drm/tegra: dc: Support memory bandwidth management Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 45/52] drm/tegra: dc: Extend debug stats with total number of events Dmitry Osipenko
2020-10-25 22:17 ` [PATCH v6 46/52] opp: Put interconnect paths outside of opp_table_lock Dmitry Osipenko
2020-10-27 5:10 ` Viresh Kumar
2020-10-27 20:26 ` Dmitry Osipenko
2020-10-28 4:03 ` Viresh Kumar
2020-10-25 22:17 ` [PATCH v6 47/52] PM / devfreq: tegra20: Silence deferred probe error Dmitry Osipenko
2020-10-26 3:16 ` Chanwoo Choi
2020-10-25 22:17 ` [PATCH v6 48/52] PM / devfreq: tegra20: Relax Kconfig dependency Dmitry Osipenko
2020-10-26 3:18 ` Chanwoo Choi
2020-10-25 22:17 ` [PATCH v6 49/52] PM / devfreq: tegra20: Convert to EMC_STAT driver, support interconnect and device-tree Dmitry Osipenko
2020-11-01 13:31 ` Chanwoo Choi
2020-11-01 14:12 ` Dmitry Osipenko
2020-11-02 20:08 ` Dmitry Osipenko
2020-11-03 2:22 ` Chanwoo Choi
2020-10-25 22:17 ` [PATCH v6 50/52] PM / devfreq: tegra30: Silence deferred probe error Dmitry Osipenko
2020-10-26 3:17 ` Chanwoo Choi
2020-10-25 22:17 ` [PATCH v6 51/52] PM / devfreq: tegra30: Support interconnect and OPPs from device-tree Dmitry Osipenko
2020-11-01 14:39 ` Chanwoo Choi
2020-11-01 15:23 ` Dmitry Osipenko
2020-11-01 15:44 ` Chanwoo Choi
2020-11-01 15:49 ` Dmitry Osipenko
2020-11-01 15:57 ` Chanwoo Choi
2020-11-02 19:58 ` Dmitry Osipenko
2020-11-02 20:00 ` Dmitry Osipenko
2020-11-01 14:44 ` Chanwoo Choi
2020-11-01 15:24 ` Dmitry Osipenko
2020-11-01 15:45 ` Chanwoo Choi
2020-10-25 22:17 ` [PATCH v6 52/52] PM / devfreq: tegra30: Separate configurations per-SoC generation Dmitry Osipenko
2020-11-01 15:20 ` Chanwoo Choi
2020-10-26 15:08 ` [PATCH v6 00/52] Introduce memory interconnect for NVIDIA Tegra SoCs Krzysztof Kozlowski
2020-10-26 19:14 ` Dmitry Osipenko
2020-10-27 8:52 ` Krzysztof Kozlowski
2020-10-27 20:31 ` Dmitry Osipenko
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