clk: tegra: Do not return 0 on failure
diff mbox series

Message ID 20201029004820.9062-1-nicoleotsuka@gmail.com
State In Next
Commit d547b3d7a422f58b0f3c6231cdf074e2221d94c7
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  • clk: tegra: Do not return 0 on failure
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Commit Message

Nicolin Chen Oct. 29, 2020, 12:48 a.m. UTC
Return values from read_dt_param() will be either TRUE (1) or
FALSE (0), while dfll_fetch_pwm_params() returns 0 on success
or an ERR code on failure.

So this patch fixes the bug of returning 0 on failure.

Fixes: 36541f0499fe ("clk: tegra: dfll: support PWM regulator control")
Cc: <stable@vger.kernel.org>
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
---
 drivers/clk/tegra/clk-dfll.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Thierry Reding Nov. 20, 2020, 4:16 p.m. UTC | #1
On Wed, Oct 28, 2020 at 05:48:20PM -0700, Nicolin Chen wrote:
> Return values from read_dt_param() will be either TRUE (1) or
> FALSE (0), while dfll_fetch_pwm_params() returns 0 on success
> or an ERR code on failure.
> 
> So this patch fixes the bug of returning 0 on failure.
> 
> Fixes: 36541f0499fe ("clk: tegra: dfll: support PWM regulator control")
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
>  drivers/clk/tegra/clk-dfll.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Mike, Stephen,

if you don't mind, I'll pick this up in the Tegra tree since there are a
few other Tegra clock patches on the list that may require coordination
inside the Tegra tree.

Thierry
Thierry Reding Nov. 20, 2020, 4:18 p.m. UTC | #2
On Fri, Nov 20, 2020 at 05:16:56PM +0100, Thierry Reding wrote:
> On Wed, Oct 28, 2020 at 05:48:20PM -0700, Nicolin Chen wrote:
> > Return values from read_dt_param() will be either TRUE (1) or
> > FALSE (0), while dfll_fetch_pwm_params() returns 0 on success
> > or an ERR code on failure.
> > 
> > So this patch fixes the bug of returning 0 on failure.
> > 
> > Fixes: 36541f0499fe ("clk: tegra: dfll: support PWM regulator control")
> > Cc: <stable@vger.kernel.org>
> > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> > ---
> >  drivers/clk/tegra/clk-dfll.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> Mike, Stephen,
> 
> if you don't mind, I'll pick this up in the Tegra tree since there are a
> few other Tegra clock patches on the list that may require coordination
> inside the Tegra tree.

Also, I do plan on sending the collected set of patches to you for
inclusion via PR at a later date, if that's okay with you.

Thierry
Stephen Boyd Nov. 25, 2020, 2:06 a.m. UTC | #3
Quoting Thierry Reding (2020-11-20 08:18:39)
> On Fri, Nov 20, 2020 at 05:16:56PM +0100, Thierry Reding wrote:
> > On Wed, Oct 28, 2020 at 05:48:20PM -0700, Nicolin Chen wrote:
> > > Return values from read_dt_param() will be either TRUE (1) or
> > > FALSE (0), while dfll_fetch_pwm_params() returns 0 on success
> > > or an ERR code on failure.
> > > 
> > > So this patch fixes the bug of returning 0 on failure.
> > > 
> > > Fixes: 36541f0499fe ("clk: tegra: dfll: support PWM regulator control")
> > > Cc: <stable@vger.kernel.org>
> > > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> > > ---
> > >  drivers/clk/tegra/clk-dfll.c | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > Mike, Stephen,
> > 
> > if you don't mind, I'll pick this up in the Tegra tree since there are a
> > few other Tegra clock patches on the list that may require coordination
> > inside the Tegra tree.
> 
> Also, I do plan on sending the collected set of patches to you for
> inclusion via PR at a later date, if that's okay with you.
> 

Ok sure.

Patch
diff mbox series

diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
index cfbaa90c7adb..a5f526bb0483 100644
--- a/drivers/clk/tegra/clk-dfll.c
+++ b/drivers/clk/tegra/clk-dfll.c
@@ -1856,13 +1856,13 @@  static int dfll_fetch_pwm_params(struct tegra_dfll *td)
 			    &td->reg_init_uV);
 	if (!ret) {
 		dev_err(td->dev, "couldn't get initialized voltage\n");
-		return ret;
+		return -EINVAL;
 	}
 
 	ret = read_dt_param(td, "nvidia,pwm-period-nanoseconds", &pwm_period);
 	if (!ret) {
 		dev_err(td->dev, "couldn't get PWM period\n");
-		return ret;
+		return -EINVAL;
 	}
 	td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1);