From: "Ramuthevar,Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com>
To: broonie@kernel.org, vigneshr@ti.com, tudor.ambarus@microchip.com,
linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
robh+dt@kernel.org
Cc: devicetree@vger.kernel.org, miquel.raynal@bootlin.com,
simon.k.r.goldschmidt@gmail.com, dinguyen@kernel.org,
richard@nod.at, cheol.yong.kim@intel.com, qi-ming.wu@intel.com,
Ramuthevar Vadivel Murugan
<vadivel.muruganx.ramuthevar@linux.intel.com>
Subject: [PATCH v5 3/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
Date: Thu, 29 Oct 2020 14:20:11 +0800 [thread overview]
Message-ID: <20201029062014.27620-4-vadivel.muruganx.ramuthevar@linux.intel.com> (raw)
In-Reply-To: <20201029062014.27620-1-vadivel.muruganx.ramuthevar@linux.intel.com>
From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Add multiple chipselect support for Intel LGM SoCs,
currently QSPI-NOR and QSPI-NAND supported.
Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
---
drivers/spi/spi-cadence-quadspi.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 6d6f7c440ece..c4440797db43 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -38,6 +38,7 @@
/* Capabilities */
#define CQSPI_SUPPORTS_OCTAL BIT(0)
+#define CQSPI_SUPPORTS_MULTI_CHIPSELECT BIT(1)
struct cqspi_st;
@@ -75,6 +76,7 @@ struct cqspi_st {
bool is_decoded_cs;
u32 fifo_depth;
u32 fifo_width;
+ u32 num_chipselect;
bool rclk_en;
u32 trigger_address;
u32 wr_delay;
@@ -1049,6 +1051,7 @@ static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
{
+ const struct cqspi_driver_platdata *ddata;
struct device *dev = &cqspi->pdev->dev;
struct device_node *np = dev->of_node;
@@ -1070,6 +1073,15 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
return -ENXIO;
}
+ ddata = of_device_get_match_data(dev);
+ if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT) {
+ if (of_property_read_u32(np, "num-chipselect",
+ &cqspi->num_chipselect)) {
+ dev_err(dev, "couldn't determine number of cs\n");
+ return -ENXIO;
+ }
+ }
+
cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
return 0;
@@ -1307,6 +1319,9 @@ static int cqspi_probe(struct platform_device *pdev)
cqspi->current_cs = -1;
cqspi->sclk = 0;
+ if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT)
+ master->num_chipselect = cqspi->num_chipselect;
+
ret = cqspi_setup_flash(cqspi);
if (ret) {
dev_err(dev, "failed to setup flash parameters %d\n", ret);
@@ -1396,6 +1411,7 @@ static const struct cqspi_driver_platdata am654_ospi = {
};
static const struct cqspi_driver_platdata intel_lgm_qspi = {
+ .hwcaps_mask = CQSPI_SUPPORTS_MULTI_CHIPSELECT,
.quirks = CQSPI_DISABLE_DAC_MODE,
};
--
2.11.0
next prev parent reply other threads:[~2020-10-29 7:35 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-29 6:20 [PATCH v5 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-10-29 6:20 ` [PATCH v5 1/6] spi: cadence-quadspi: Add QSPI " Ramuthevar,Vadivel MuruganX
2020-10-29 6:20 ` [PATCH v5 2/6] spi: cadence-quadspi: Disable the DAC " Ramuthevar,Vadivel MuruganX
2020-10-29 6:20 ` Ramuthevar,Vadivel MuruganX [this message]
2020-10-29 6:20 ` [PATCH v5 4/6] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi Ramuthevar,Vadivel MuruganX
2020-10-29 6:20 ` [PATCH v5 5/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml Ramuthevar,Vadivel MuruganX
2020-10-29 15:59 ` Rob Herring
2020-10-29 22:14 ` Ramuthevar, Vadivel MuruganX
2020-11-05 7:14 ` Linus Walleij
2020-11-06 4:43 ` Ramuthevar, Vadivel MuruganX
2020-10-29 6:20 ` [PATCH v5 6/6] dt-bindings: spi: Add compatible for Intel LGM SoC Ramuthevar,Vadivel MuruganX
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