From: Marek Szyprowski <m.szyprowski@samsung.com>
To: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Jaehoon Chung <jh80.chung@samsung.com>,
Marek Szyprowski <m.szyprowski@samsung.com>,
Jingoo Han <jingoohan1@gmail.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Rob Herring <robh@kernel.org>
Subject: [PATCH v3 1/6] dt-bindings: pci: drop samsung,exynos5440-pcie binding
Date: Thu, 29 Oct 2020 14:40:12 +0100 [thread overview]
Message-ID: <20201029134017.27400-2-m.szyprowski@samsung.com> (raw)
In-Reply-To: <20201029134017.27400-1-m.szyprowski@samsung.com>
Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
dts: exynos: Remove Exynos5440"). Drop the obsolete bindings for
exynos5440-pcie.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
---
.../bindings/pci/samsung,exynos5440-pcie.txt | 58 -------------------
1 file changed, 58 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
deleted file mode 100644
index 651d957d1051..000000000000
--- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-* Samsung Exynos 5440 PCIe interface
-
-This PCIe host controller is based on the Synopsys DesignWare PCIe IP
-and thus inherits all the common properties defined in designware-pcie.txt.
-
-Required properties:
-- compatible: "samsung,exynos5440-pcie"
-- reg: base addresses and lengths of the PCIe controller,
-- reg-names : First name should be set to "elbi".
- And use the "config" instead of getting the configuration address space
- from "ranges".
- NOTE: When using the "config" property, reg-names must be set.
-- interrupts: A list of interrupt outputs for level interrupt,
- pulse interrupt, special interrupt.
-- phys: From PHY binding. Phandle for the generic PHY.
- Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
-
-For other common properties, refer to
- Documentation/devicetree/bindings/pci/designware-pcie.txt
-
-Example:
-
-SoC-specific DT Entry (with using PHY framework):
-
- pcie_phy0: pcie-phy@270000 {
- ...
- reg = <0x270000 0x1000>, <0x271000 0x40>;
- reg-names = "phy", "block";
- ...
- };
-
- pcie@290000 {
- compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
- reg = <0x290000 0x1000>, <0x40000000 0x1000>;
- reg-names = "elbi", "config";
- clocks = <&clock 28>, <&clock 27>;
- clock-names = "pcie", "pcie_bus";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- phys = <&pcie_phy0>;
- ranges = <0x81000000 0 0 0x60001000 0 0x00010000
- 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- num-lanes = <4>;
- };
-
-Board-specific DT Entry:
-
- pcie@290000 {
- reset-gpio = <&pin_ctrl 5 0>;
- };
-
- pcie@2a0000 {
- reset-gpio = <&pin_ctrl 22 0>;
- };
--
2.17.1
next prev parent reply other threads:[~2020-10-29 13:42 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20201029134037eucas1p17f861adc0858e8a80d516dc0f2733f84@eucas1p1.samsung.com>
2020-10-29 13:40 ` [PATCH v3 0/6] Add DW PCIe support for Exynos5433 SoCs Marek Szyprowski
[not found] ` <CGME20201029134037eucas1p275bad9fe08eff145711cc36ac8c685f7@eucas1p2.samsung.com>
2020-10-29 13:40 ` Marek Szyprowski [this message]
[not found] ` <CGME20201029134038eucas1p28d9bd33bc9e36b960b021a40ef299b47@eucas1p2.samsung.com>
2020-10-29 13:40 ` [PATCH v3 2/6] dt-bindings: pci: add the samsung,exynos-pcie binding Marek Szyprowski
2020-11-04 21:35 ` Rob Herring
2020-11-05 8:33 ` Marek Szyprowski
2020-11-05 15:27 ` Rob Herring
2020-11-05 17:14 ` Jingoo Han
[not found] ` <CGME20201029134038eucas1p2d550a45ff3222ccb72d15d5c89d4f938@eucas1p2.samsung.com>
2020-10-29 13:40 ` [PATCH v3 3/6] dt-bindings: phy: add the samsung,exynos-pcie-phy binding Marek Szyprowski
2020-11-04 21:39 ` Rob Herring
[not found] ` <CGME20201029134039eucas1p2270e5f4ecea05b17f4d9107300ce946d@eucas1p2.samsung.com>
2020-10-29 13:40 ` [PATCH v3 4/6] phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY Marek Szyprowski
[not found] ` <CGME20201029134040eucas1p1d9ab30c75ac9243346b4786e7048d6be@eucas1p1.samsung.com>
2020-10-29 13:40 ` [PATCH v3 5/6] pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant Marek Szyprowski
2020-10-29 21:59 ` Jingoo Han
2020-11-04 21:39 ` Rob Herring
[not found] ` <CGME20201029134040eucas1p2a8958b44842a8a4647e3aa4521c75725@eucas1p2.samsung.com>
2020-10-29 13:40 ` [PATCH v3 6/6] arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards Marek Szyprowski
2020-11-05 19:14 ` Krzysztof Kozlowski
2020-11-03 22:44 ` [PATCH v3 0/6] Add DW PCIe support for Exynos5433 SoCs Bjorn Helgaas
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