From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>
Cc: Swapnil Kashinath Jakhade <sjakhade@cadence.com>,
Milind Parab <mparab@cadence.com>,
Yuti Suresh Amonkar <yamonkar@cadence.com>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Subject: [PATCH 1/9] dt-bindings: phy: cadence-sierra: Add bindings for the PLLs within SERDES
Date: Tue, 3 Nov 2020 09:25:48 +0530 [thread overview]
Message-ID: <20201103035556.21260-2-kishon@ti.com> (raw)
In-Reply-To: <20201103035556.21260-1-kishon@ti.com>
Add binding for the PLLs within SERDES.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
.../bindings/phy/phy-cadence-sierra.yaml | 89 ++++++++++++++++++-
1 file changed, 86 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
index d210843863df..f574b8ed358c 100644
--- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
@@ -49,12 +49,14 @@ properties:
const: serdes
clocks:
- maxItems: 2
+ maxItems: 4
clock-names:
items:
- const: cmn_refclk_dig_div
- const: cmn_refclk1_dig_div
+ - const: pll_cmnlc
+ - const: pll_cmnlc1
cdns,autoconf:
type: boolean
@@ -107,6 +109,58 @@ patternProperties:
additionalProperties: false
+ "^refrcv1?$":
+ type: object
+ description: |
+ Reference receivers that enables routing external clocks to the alternate
+ PLLCMNLC.
+ properties:
+ clocks:
+ maxItems: 1
+ description: Phandle to clock nodes representing the input to the
+ reference receiver.
+
+ clock-names:
+ items:
+ - const: pll_refclk
+
+ "#clock-cells":
+ const: 0
+
+ required:
+ - clocks
+ - "#clock-cells"
+
+ "^pll_cmnlc1?$":
+ type: object
+ description: |
+ SERDES node should have subnodes for each of the PLLs present in
+ the SERDES.
+ properties:
+ clocks:
+ maxItems: 2
+ description: Phandle to clock nodes representing the two inputs to PLL.
+
+ clock-names:
+ items:
+ - const: pll_refclk
+ - const: refrcv
+
+ "#clock-cells":
+ const: 0
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-parents:
+ maxItems: 1
+
+ required:
+ - clocks
+ - "#clock-cells"
+ - assigned-clocks
+ - assigned-clock-parents
+
required:
- compatible
- "#address-cells"
@@ -130,10 +184,39 @@ examples:
reg = <0x0 0xfd240000 0x0 0x40000>;
resets = <&phyrst 0>, <&phyrst 1>;
reset-names = "sierra_reset", "sierra_apb";
- clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>, <&serdes_pll_cmnlc>, <&serdes_pll_cmnlc1>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1";
#address-cells = <1>;
#size-cells = <0>;
+
+ serdes_refrcv: refrcv {
+ clocks = <&pll0_refclk>;
+ clock-names = "pll_refclk";
+ #clock-cells = <0>;
+ };
+
+ serdes_refrcv1: refrcv1 {
+ clocks = <&pll1_refclk>;
+ clock-names = "pll_refclk";
+ #clock-cells = <0>;
+ };
+
+ serdes_pll_cmnlc: pll_cmnlc {
+ clocks = <&pll0_refclk>, <&serdes_refrcv1>;
+ clock-names = "pll_refclk", "refrcv";
+ #clock-cells = <0>;
+ assigned-clocks = <&serdes_pll_cmnlc>;
+ assigned-clock-parents = <&pll0_refclk>;
+ };
+
+ serdes_pll_cmnlc1: pll_cmnlc1 {
+ clocks = <&pll1_refclk>, <&serdes_refrcv>;
+ clock-names = "pll_refclk", "refrcv";
+ #clock-cells = <0>;
+ assigned-clocks = <&serdes_pll_cmnlc1>;
+ assigned-clock-parents = <&pll1_refclk>;
+ };
+
pcie0_phy0: phy@0 {
reg = <0>;
resets = <&phyrst 2>;
--
2.17.1
next prev parent reply other threads:[~2020-11-03 3:56 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-03 3:55 [PATCH 0/9] PHY: Enhance Sierra SERDES Kishon Vijay Abraham I
2020-11-03 3:55 ` Kishon Vijay Abraham I [this message]
2020-11-05 18:03 ` [PATCH 1/9] dt-bindings: phy: cadence-sierra: Add bindings for the PLLs within SERDES Rob Herring
2020-12-21 3:10 ` Kishon Vijay Abraham I
2020-11-03 3:55 ` [PATCH 2/9] phy: ti: j721e-wiz: Get PHY properties only for "phy" subnode Kishon Vijay Abraham I
2020-11-03 3:55 ` [PATCH 3/9] phy: ti: j721e-wiz: Don't configure wiz if its already configured Kishon Vijay Abraham I
2020-11-16 7:30 ` Vinod Koul
2021-03-09 12:13 ` Kishon Vijay Abraham I
2020-11-03 3:55 ` [PATCH 4/9] phy: cadence: cadence-sierra: Create PHY only for "phy" sub-nodes Kishon Vijay Abraham I
2020-11-03 3:55 ` [PATCH 5/9] phy: cadence: Sierra: Fix PHY power_on sequence Kishon Vijay Abraham I
2020-11-16 7:32 ` Vinod Koul
2020-11-03 3:55 ` [PATCH 6/9] phy: cadence: sierra: Don't configure if any plls are already locked Kishon Vijay Abraham I
2020-11-09 8:39 ` Philipp Zabel
2020-11-03 3:55 ` [PATCH 7/9] phy: cadence: sierra: Model reference receiver as clocks (gate clocks) Kishon Vijay Abraham I
2020-11-03 3:55 ` [PATCH 8/9] phy: cadence: sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks) Kishon Vijay Abraham I
2020-11-03 3:55 ` [PATCH 9/9] phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks Kishon Vijay Abraham I
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