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From: Tiezhu Yang <yangtiezhu@loongson.cn>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Huacai Chen <chenhc@lemote.com>,
	Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
	Xuefeng Li <lixuefeng@loongson.cn>, Lu Zeng <zenglu@loongson.cn>,
	Jun Yi <yijun@loongson.cn>
Subject: [PATCH v3 5/6] MIPS: Loongson64: SMP: Fix up play_dead jump indicator
Date: Tue,  3 Nov 2020 15:12:04 +0800	[thread overview]
Message-ID: <1604387525-23400-6-git-send-email-yangtiezhu@loongson.cn> (raw)
In-Reply-To: <1604387525-23400-1-git-send-email-yangtiezhu@loongson.cn>

In play_dead function, the whole 64-bit PC mailbox was used as a indicator
to determine if the master core had written boot jump information.

However, after we introduced CSR mailsend, the hardware will not guarante
an atomic write for the 64-bit PC mailbox. Thus we have to use the lower
32-bit which is written at the last as the jump indicator instead.

Signed-off-by: Lu Zeng <zenglu@loongson.cn>
Signed-off-by: Jun Yi <yijun@loongson.cn>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
---

v2: No changes
v3: Update the commit message and comment

 arch/mips/loongson64/smp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index 736e98d..aa0cd72 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -764,9 +764,10 @@ static void loongson3_type3_play_dead(int *state_addr)
 		"1: li    %[count], 0x100             \n" /* wait for init loop */
 		"2: bnez  %[count], 2b                \n" /* limit mailbox access */
 		"   addiu %[count], -1                \n"
-		"   ld    %[initfunc], 0x20(%[base])  \n" /* get PC via mailbox */
+		"   lw    %[initfunc], 0x20(%[base])  \n" /* check lower 32-bit as jump indicator */
 		"   beqz  %[initfunc], 1b             \n"
 		"   nop                               \n"
+		"   ld    %[initfunc], 0x20(%[base])  \n" /* get PC (whole 64-bit) via mailbox */
 		"   ld    $sp, 0x28(%[base])          \n" /* get SP via mailbox */
 		"   ld    $gp, 0x30(%[base])          \n" /* get GP via mailbox */
 		"   ld    $a1, 0x38(%[base])          \n"
-- 
2.1.0


  parent reply	other threads:[~2020-11-03  7:12 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-03  7:11 [PATCH v3 0/6] Modify some registers operations and move decode_cpucfg() to loongson_regs.h Tiezhu Yang
2020-11-03  7:12 ` [PATCH v3 1/6] MIPS: Loongson64: Do not write the read only field LPA of CP0_CONFIG3 Tiezhu Yang
2020-11-04  2:00   ` Huacai Chen
2020-11-04  3:50     ` Tiezhu Yang
2020-11-05  5:57       ` Huacai Chen
2020-11-05  9:05         ` Tiezhu Yang
2020-11-03  7:12 ` [PATCH v3 2/6] MIPS: Loongson64: Set the field ELPA of CP0_PAGEGRAIN only once Tiezhu Yang
2020-11-03  7:12 ` [PATCH v3 3/6] MIPS: Loongson64: Set IPI_Enable register per core by itself Tiezhu Yang
2020-11-03  7:12 ` [PATCH v3 4/6] MIPS: Loongson64: Add Mail_Send support for 3A4000+ CPU Tiezhu Yang
2020-11-03  7:12 ` Tiezhu Yang [this message]
2020-11-04  6:31   ` [PATCH v3 5/6] MIPS: Loongson64: SMP: Fix up play_dead jump indicator Jinyang He
2020-11-04  7:04     ` Jiaxun Yang
2020-11-04  7:18       ` Jinyang He
2020-11-03  7:12 ` [PATCH v3 6/6] MIPS: Loongson64: Move decode_cpucfg() to loongson_regs.h Tiezhu Yang
2020-11-11 23:05   ` Thomas Bogendoerfer
2020-11-11 23:04 ` [PATCH v3 0/6] Modify some registers operations and move " Thomas Bogendoerfer

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