From: Coiby Xu <coiby.xu@gmail.com>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>,
Hans de Goede <hdegoede@redhat.com>,
Benjamin Tissoires <benjamin.tissoires@redhat.com>,
linux-gpio@vger.kernel.org (open list:PIN CONTROL SUBSYSTEM),
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v2 4/4] pinctrl: amd: remove debounce filter setting in irq type setting
Date: Thu, 5 Nov 2020 07:07:03 +0800 [thread overview]
Message-ID: <20201104230703.21466-5-coiby.xu@gmail.com> (raw)
In-Reply-To: <20201104230703.21466-1-coiby.xu@gmail.com>
Debounce filter setting should be independent from irq type setting
because according to the ACPI specs, there are separate arguments for
specifying debounce timeout and irq type in GpioIo and GpioInt.
This will fix broken touchpads for Lenovo Legion-5 AMD gaming laptops
including 15ARH05 (R7000) and R7000P whose BIOS set the debounce timeout
to 124.8ms which led to the kernel receiving only ~7 HID reports per
second.
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Benjamin Tissoires <benjamin.tissoires@redhat.com>
BugLink: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1887190
Link: https://lore.kernel.org/linux-gpio/CAHp75VcwiGREBUJ0A06EEw-SyabqYsp%2Bdqs2DpSrhaY-2GVdAA%40mail.gmail.com/
Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
---
drivers/pinctrl/pinctrl-amd.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index e9b761c2b77a..2d4acf21117c 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -468,7 +468,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg &= ~BIT(LEVEL_TRIG_OFF);
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
- pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_edge_irq);
break;
@@ -476,7 +475,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg &= ~BIT(LEVEL_TRIG_OFF);
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
- pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_edge_irq);
break;
@@ -484,7 +482,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg &= ~BIT(LEVEL_TRIG_OFF);
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
- pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_edge_irq);
break;
@@ -492,8 +489,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
- pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
- pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_level_irq);
break;
@@ -501,8 +496,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
- pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
- pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_level_irq);
break;
--
2.28.0
next prev parent reply other threads:[~2020-11-04 23:07 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20201104230703.21466-1-coiby.xu@gmail.com>
2020-11-04 23:07 ` [PATCH v2 1/4] pinctrl: amd: fix incorrect way to disable debounce filter Coiby Xu
2020-11-04 23:07 ` [PATCH v2 2/4] pinctrl: amd: use higher precision for 512 RtcClk Coiby Xu
2020-11-05 11:13 ` Andy Shevchenko
2020-11-05 23:32 ` Coiby Xu
2020-11-04 23:07 ` [PATCH v2 3/4] pinctrl: amd: print debounce filter info in debugfs Coiby Xu
2020-11-04 23:07 ` Coiby Xu [this message]
2020-11-05 11:13 ` [PATCH v2 4/4] pinctrl: amd: remove debounce filter setting in irq type setting Andy Shevchenko
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