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From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Nicolas Boichat <drinkcat@chromium.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
	<srv_heupstream@mediatek.com>, Weiyi Lu <weiyi.lu@mediatek.com>
Subject: [PATCH v2 13/13] clk: mediatek: use en_mask as a pure div_en_mask
Date: Mon, 9 Nov 2020 10:13:28 +0800	[thread overview]
Message-ID: <1604888008-30555-14-git-send-email-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <1604888008-30555-1-git-send-email-weiyi.lu@mediatek.com>

Because all pll data has been updated. We no longer allow
en_mask to be a combination of pll_en_bit and div_en_mask.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
 drivers/clk/mediatek/clk-pll.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 11ed5d1..e0b00bc 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -238,7 +238,6 @@ static int mtk_pll_prepare(struct clk_hw *hw)
 {
 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
 	u32 r;
-	u32 div_en_mask;
 
 	r = readl(pll->pwr_addr) | CON0_PWR_ON;
 	writel(r, pll->pwr_addr);
@@ -251,9 +250,8 @@ static int mtk_pll_prepare(struct clk_hw *hw)
 	r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN;
 	writel(r, pll->base_addr + REG_CON0);
 
-	div_en_mask = pll->data->en_mask & ~CON0_BASE_EN;
-	if (div_en_mask) {
-		r = readl(pll->base_addr + REG_CON0) | div_en_mask;
+	if (pll->data->en_mask) {
+		r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
 		writel(r, pll->base_addr + REG_CON0);
 	}
 
@@ -274,7 +272,6 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
 {
 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
 	u32 r;
-	u32 div_en_mask;
 
 	if (pll->data->flags & HAVE_RST_BAR) {
 		r = readl(pll->base_addr + REG_CON0);
@@ -284,9 +281,8 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
 
 	__mtk_pll_tuner_disable(pll);
 
-	div_en_mask = pll->data->en_mask & ~CON0_BASE_EN;
-	if (div_en_mask) {
-		r = readl(pll->base_addr + REG_CON0) & ~div_en_mask;
+	if (pll->data->en_mask) {
+		r = readl(pll->base_addr + REG_CON0) & ~pll->data->en_mask;
 		writel(r, pll->base_addr + REG_CON0);
 	}
 
-- 
1.8.1.1.dirty

  parent reply	other threads:[~2020-11-09  2:14 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-09  2:13 [PATCH v2 00/13] Clean up the pll_en_bit from en_mask on all the MediaTek clock drivers Weiyi Lu
2020-11-09  2:13 ` [PATCH v2 01/13] clk: mediatek: Clean up the pll_en_bit from en_mask on MT2701 Weiyi Lu
2020-11-09  2:13 ` [PATCH v2 02/13] clk: mediatek: Clean up the pll_en_bit from en_mask on MT2712 Weiyi Lu
2020-11-09  2:13 ` [PATCH v2 03/13] clk: mediatek: Clean up the pll_en_bit from en_mask on MT6765 Weiyi Lu
2020-11-09  2:13 ` [PATCH v2 04/13] clk: mediatek: Clean up the pll_en_bit from en_mask on MT6779 Weiyi Lu
2020-11-09  2:13 ` [PATCH v2 05/13] clk: mediatek: Clean up the pll_en_bit from en_mask on MT6797 Weiyi Lu
2020-11-09  2:13 ` [PATCH v2 06/13] clk: mediatek: Clean up the pll_en_bit from en_mask on MT7622 Weiyi Lu
2020-11-09  2:13 ` [PATCH v2 07/13] clk: mediatek: Clean up the pll_en_bit from en_mask on MT7629 Weiyi Lu
2020-11-09  2:13 ` [PATCH v2 08/13] clk: mediatek: Clean up the pll_en_bit from en_mask on MT8135 Weiyi Lu
2020-11-09  2:13 ` [PATCH v2 09/13] clk: mediatek: Clean up the pll_en_bit from en_mask on MT8167 Weiyi Lu
2020-11-09  2:13 ` [PATCH v2 10/13] clk: mediatek: Clean up the pll_en_bit from en_mask on MT8173 Weiyi Lu
2020-11-09  2:13 ` [PATCH v2 11/13] clk: mediatek: Clean up the pll_en_bit from en_mask on MT8183 Weiyi Lu
2020-11-09  2:13 ` [PATCH v2 12/13] clk: mediatek: Clean up the pll_en_bit from en_mask on MT8516 Weiyi Lu
2020-11-09  2:13 ` Weiyi Lu [this message]
2020-12-17  9:17 ` [PATCH v2 00/13] Clean up the pll_en_bit from en_mask on all the MediaTek clock drivers Stephen Boyd

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