From: Marek Szyprowski <m.szyprowski@samsung.com>
To: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Jaehoon Chung <jh80.chung@samsung.com>,
Marek Szyprowski <m.szyprowski@samsung.com>,
Jingoo Han <jingoohan1@gmail.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Rob Herring <robh@kernel.org>,
Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Subject: [PATCH v4 1/5] dt-bindings: PCI: exynos: drop samsung,exynos5440-pcie binding
Date: Fri, 13 Nov 2020 18:01:35 +0100 [thread overview]
Message-ID: <20201113170139.29956-2-m.szyprowski@samsung.com> (raw)
In-Reply-To: <20201113170139.29956-1-m.szyprowski@samsung.com>
Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
dts: exynos: Remove Exynos5440"). Drop the obsolete bindings for
exynos5440-pcie.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
---
.../bindings/pci/samsung,exynos5440-pcie.txt | 58 -------------------
1 file changed, 58 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
deleted file mode 100644
index 651d957d1051..000000000000
--- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-* Samsung Exynos 5440 PCIe interface
-
-This PCIe host controller is based on the Synopsys DesignWare PCIe IP
-and thus inherits all the common properties defined in designware-pcie.txt.
-
-Required properties:
-- compatible: "samsung,exynos5440-pcie"
-- reg: base addresses and lengths of the PCIe controller,
-- reg-names : First name should be set to "elbi".
- And use the "config" instead of getting the configuration address space
- from "ranges".
- NOTE: When using the "config" property, reg-names must be set.
-- interrupts: A list of interrupt outputs for level interrupt,
- pulse interrupt, special interrupt.
-- phys: From PHY binding. Phandle for the generic PHY.
- Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
-
-For other common properties, refer to
- Documentation/devicetree/bindings/pci/designware-pcie.txt
-
-Example:
-
-SoC-specific DT Entry (with using PHY framework):
-
- pcie_phy0: pcie-phy@270000 {
- ...
- reg = <0x270000 0x1000>, <0x271000 0x40>;
- reg-names = "phy", "block";
- ...
- };
-
- pcie@290000 {
- compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
- reg = <0x290000 0x1000>, <0x40000000 0x1000>;
- reg-names = "elbi", "config";
- clocks = <&clock 28>, <&clock 27>;
- clock-names = "pcie", "pcie_bus";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- phys = <&pcie_phy0>;
- ranges = <0x81000000 0 0 0x60001000 0 0x00010000
- 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- num-lanes = <4>;
- };
-
-Board-specific DT Entry:
-
- pcie@290000 {
- reset-gpio = <&pin_ctrl 5 0>;
- };
-
- pcie@2a0000 {
- reset-gpio = <&pin_ctrl 22 0>;
- };
--
2.17.1
next prev parent reply other threads:[~2020-11-13 17:02 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20201113170156eucas1p176314e4076c593d1f2e68159be880f86@eucas1p1.samsung.com>
2020-11-13 17:01 ` [PATCH v4 0/5] Add DW PCIe support for Exynos5433 SoCs Marek Szyprowski
[not found] ` <CGME20201113170156eucas1p27318509e20996cd7b774a991bbd729c6@eucas1p2.samsung.com>
2020-11-13 17:01 ` Marek Szyprowski [this message]
[not found] ` <CGME20201113170157eucas1p1586185df931144982527eb3aa988a127@eucas1p1.samsung.com>
2020-11-13 17:01 ` [PATCH v4 2/5] dt-bindings: PCI: exynos: add the samsung,exynos-pcie binding Marek Szyprowski
[not found] ` <CGME20201113170158eucas1p1a1fa871bfc1513e3bb62b56c28454e68@eucas1p1.samsung.com>
2020-11-13 17:01 ` [PATCH v4 3/5] dt-bindings: phy: exynos: add the samsung,exynos-pcie-phy binding Marek Szyprowski
[not found] ` <CGME20201113170158eucas1p14b9e58e35f929e14aeb4f533071c8a47@eucas1p1.samsung.com>
2020-11-13 17:01 ` [PATCH v4 4/5] phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY Marek Szyprowski
2020-11-20 9:41 ` Vinod Koul
2020-11-20 9:58 ` Marek Szyprowski
2020-11-20 10:11 ` Vinod Koul
[not found] ` <CGME20201120102654eucas1p2f7395e14632a019a58f0ed5002eff556@eucas1p2.samsung.com>
2020-11-20 10:26 ` [PATCH v4 4/5 REBASED RESEND] " Marek Szyprowski
2020-11-20 10:36 ` Vinod Koul
[not found] ` <CGME20201113170159eucas1p2a479cba641c51368e0f15b6f8eaeb5f4@eucas1p2.samsung.com>
2020-11-13 17:01 ` [PATCH v4 5/5] PCI: dwc: exynos: Rework the driver to support Exynos5433 variant Marek Szyprowski
2020-11-23 9:53 ` [PATCH v4 0/5] Add DW PCIe support for Exynos5433 SoCs Lorenzo Pieralisi
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