From: matthew.gerlach@linux.intel.com
To: linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org,
mdf@kernel.org, hao.wu@intel.com, trix@redhat.com,
linux-doc@vger.kernel.org, corbet@lwn.net
Cc: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Subject: [PATCH 1/2] fpga: dfl: refactor cci_enumerate_feature_devs()
Date: Mon, 16 Nov 2020 17:25:51 -0800 [thread overview]
Message-ID: <20201117012552.262149-2-matthew.gerlach@linux.intel.com> (raw)
In-Reply-To: <20201117012552.262149-1-matthew.gerlach@linux.intel.com>
From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
In preparation of looking for dfls based on a vendor
specific pcie capability, move code that assumes
Bar0/offset0 as start of DFL to its own function.
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
drivers/fpga/dfl-pci.c | 86 ++++++++++++++++++++++++------------------
1 file changed, 49 insertions(+), 37 deletions(-)
diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
index a2203d03c9e2..b1b157b41942 100644
--- a/drivers/fpga/dfl-pci.c
+++ b/drivers/fpga/dfl-pci.c
@@ -119,49 +119,20 @@ static int *cci_pci_create_irq_table(struct pci_dev *pcidev, unsigned int nvec)
return table;
}
-/* enumerate feature devices under pci device */
-static int cci_enumerate_feature_devs(struct pci_dev *pcidev)
+static int find_dfl_in_bar0(struct pci_dev *pcidev,
+ struct dfl_fpga_enum_info *info)
{
- struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
- int port_num, bar, i, nvec, ret = 0;
- struct dfl_fpga_enum_info *info;
- struct dfl_fpga_cdev *cdev;
resource_size_t start, len;
+ int port_num, bar, i;
void __iomem *base;
- int *irq_table;
+ int ret = 0;
u32 offset;
u64 v;
- /* allocate enumeration info via pci_dev */
- info = dfl_fpga_enum_info_alloc(&pcidev->dev);
- if (!info)
- return -ENOMEM;
-
- /* add irq info for enumeration if the device support irq */
- nvec = cci_pci_alloc_irq(pcidev);
- if (nvec < 0) {
- dev_err(&pcidev->dev, "Fail to alloc irq %d.\n", nvec);
- ret = nvec;
- goto enum_info_free_exit;
- } else if (nvec) {
- irq_table = cci_pci_create_irq_table(pcidev, nvec);
- if (!irq_table) {
- ret = -ENOMEM;
- goto irq_free_exit;
- }
-
- ret = dfl_fpga_enum_info_add_irq(info, nvec, irq_table);
- kfree(irq_table);
- if (ret)
- goto irq_free_exit;
- }
-
- /* start to find Device Feature List in Bar 0 */
+ /* start to find Device Feature List from Bar 0 */
base = cci_pci_ioremap_bar0(pcidev);
- if (!base) {
- ret = -ENOMEM;
- goto irq_free_exit;
- }
+ if (!base)
+ return -ENOMEM;
/*
* PF device has FME and Ports/AFUs, and VF device only has one
@@ -208,12 +179,53 @@ static int cci_enumerate_feature_devs(struct pci_dev *pcidev)
dfl_fpga_enum_info_add_dfl(info, start, len);
} else {
ret = -ENODEV;
- goto irq_free_exit;
}
/* release I/O mappings for next step enumeration */
pcim_iounmap_regions(pcidev, BIT(0));
+
+ return ret;
+}
+
+/* enumerate feature devices under pci device */
+static int cci_enumerate_feature_devs(struct pci_dev *pcidev)
+{
+ struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
+ struct dfl_fpga_enum_info *info;
+ struct dfl_fpga_cdev *cdev;
+ int nvec, ret = 0;
+ int *irq_table;
+
+ /* allocate enumeration info via pci_dev */
+ info = dfl_fpga_enum_info_alloc(&pcidev->dev);
+ if (!info)
+ return -ENOMEM;
+
+ /* add irq info for enumeration if the device support irq */
+ nvec = cci_pci_alloc_irq(pcidev);
+ if (nvec < 0) {
+ dev_err(&pcidev->dev, "Fail to alloc irq %d.\n", nvec);
+ ret = nvec;
+ goto enum_info_free_exit;
+ } else if (nvec) {
+ irq_table = cci_pci_create_irq_table(pcidev, nvec);
+ if (!irq_table) {
+ ret = -ENOMEM;
+ goto irq_free_exit;
+ }
+
+ ret = dfl_fpga_enum_info_add_irq(info, nvec, irq_table);
+ kfree(irq_table);
+ if (ret)
+ goto irq_free_exit;
+ }
+
+ ret = find_dfl_in_bar0(pcidev, info);
+
+ if (ret)
+ goto irq_free_exit;
+
/* start enumeration with prepared enumeration information */
cdev = dfl_fpga_feature_devs_enumerate(info);
if (IS_ERR(cdev)) {
--
2.25.2
next prev parent reply other threads:[~2020-11-17 1:24 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-17 1:25 [PATCH 0/2] fpga: dfl: optional VSEC for start of dfl matthew.gerlach
2020-11-17 1:25 ` matthew.gerlach [this message]
2020-11-17 10:05 ` [PATCH 1/2] fpga: dfl: refactor cci_enumerate_feature_devs() Wu, Hao
2020-11-17 18:05 ` matthew.gerlach
2020-11-17 20:01 ` Tom Rix
2020-11-17 1:25 ` [PATCH 2/2] fpga: dfl: look for vendor specific capability matthew.gerlach
2020-11-17 7:56 ` Xu Yilun
2020-11-17 10:00 ` Wu, Hao
2020-11-17 19:41 ` matthew.gerlach
2020-11-18 6:19 ` Xu Yilun
2020-11-17 9:47 ` Wu, Hao
2020-11-17 20:09 ` matthew.gerlach
2020-11-18 1:54 ` Wu, Hao
2020-11-18 17:49 ` matthew.gerlach
2020-11-17 14:33 ` kernel test robot
2020-11-17 20:35 ` Tom Rix
2020-11-17 23:10 ` matthew.gerlach
2020-11-18 1:29 ` Tom Rix
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