From: Sia Jee Heng <jee.heng.sia@intel.com>
To: vkoul@kernel.org, Eugeniy.Paltsev@synopsys.com, robh+dt@kernel.org
Cc: andriy.shevchenko@linux.intel.com, dmaengine@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: [PATCH v5 11/16] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields
Date: Mon, 23 Nov 2020 10:34:47 +0800 [thread overview]
Message-ID: <20201123023452.7894-12-jee.heng.sia@intel.com> (raw)
In-Reply-To: <20201123023452.7894-1-jee.heng.sia@intel.com>
Add support for Intel KeemBay DMA registers. These registers are required
to run data transfer between device to memory and memory to device on Intel
KeemBay SoC.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 46baf93de617..3a357f7fda02 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -63,6 +63,7 @@ struct axi_dma_chip {
struct device *dev;
int irq;
void __iomem *regs;
+ void __iomem *apb_regs;
struct clk *core_clk;
struct clk *cfgr_clk;
struct dw_axi_dma *dw;
@@ -169,6 +170,19 @@ static inline struct axi_dma_chan *dchan_to_axi_dma_chan(struct dma_chan *dchan)
#define CH_INTSIGNAL_ENA 0x090 /* R/W Chan Interrupt Signal Enable */
#define CH_INTCLEAR 0x098 /* W Chan Interrupt Clear */
+/* These Apb registers are used by Intel KeemBay SoC */
+#define DMAC_APB_CFG 0x000 /* DMAC Apb Configuration Register */
+#define DMAC_APB_STAT 0x004 /* DMAC Apb Status Register */
+#define DMAC_APB_DEBUG_STAT_0 0x008 /* DMAC Apb Debug Status Register 0 */
+#define DMAC_APB_DEBUG_STAT_1 0x00C /* DMAC Apb Debug Status Register 1 */
+#define DMAC_APB_HW_HS_SEL_0 0x010 /* DMAC Apb HW HS register 0 */
+#define DMAC_APB_HW_HS_SEL_1 0x014 /* DMAC Apb HW HS register 1 */
+#define DMAC_APB_LPI 0x018 /* DMAC Apb Low Power Interface Reg */
+#define DMAC_APB_BYTE_WR_CH_EN 0x01C /* DMAC Apb Byte Write Enable */
+#define DMAC_APB_HALFWORD_WR_CH_EN 0x020 /* DMAC Halfword write enables */
+
+#define UNUSED_CHANNEL 0x3F /* Set unused DMA channel to 0x3F */
+#define MAX_BLOCK_SIZE 0x1000 /* 1024 blocks * 4 bytes data width */
/* DMAC_CFG */
#define DMAC_EN_POS 0
--
2.18.0
next prev parent reply other threads:[~2020-11-23 2:52 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-23 2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 01/16] dt-bindings: dma: Add YAML schemas for dw-axi-dmac Sia Jee Heng
2020-11-30 22:25 ` Rob Herring
2020-12-09 3:21 ` Sia, Jee Heng
2020-12-10 1:22 ` Sia, Jee Heng
2020-11-23 2:34 ` [PATCH v5 02/16] dmaengine: dw-axi-dmac: simplify descriptor management Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 03/16] dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources() Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 04/16] dmaengine: dw-axi-dmac: Add device_synchronize() callback Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 05/16] dmaengine: dw-axi-dmac: Add device_config operation Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 06/16] dmaengine: dw-axi-dmac: Support device_prep_slave_sg Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 07/16] dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic() Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 08/16] dmaengine: dw-axi-dmac: Support of_dma_controller_register() Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 09/16] dmaengine: dw-axi-dmac: Support burst residue granularity Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 10/16] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA Sia Jee Heng
2020-11-30 22:29 ` Rob Herring
2020-12-09 1:53 ` Sia, Jee Heng
2020-11-23 2:34 ` Sia Jee Heng [this message]
2020-11-23 2:34 ` [PATCH v5 12/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 13/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 14/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 15/16] dmaengine: dw-axi-dmac: Set constraint to the Max segment size Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 16/16] dmaengine: dw-axi-dmac: Virtually split the linked-list Sia Jee Heng
2020-11-23 10:22 ` Andy Shevchenko
2020-12-09 1:47 ` Sia, Jee Heng
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