From: "Rafael J. Wysocki" <rjw@rjwysocki.net>
To: Linux ACPI <linux-acpi@vger.kernel.org>
Cc: LKML <linux-kernel@vger.kernel.org>
Subject: [PATCH 1/5] ACPI: EC: Fold acpi_ec_clear_gpe() into its caller
Date: Mon, 23 Nov 2020 20:37:06 +0100 [thread overview]
Message-ID: <8467712.e8rTiVh5pU@kreacher> (raw)
In-Reply-To: <3259005.CeRvrUlyd7@kreacher>
From: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
Fold acpi_ec_clear_gpe() which is only used in one place into its
caller and clean up comments related to that function while at it.
No intentional functional impact.
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
drivers/acpi/ec.c | 35 +++++++++++++----------------------
1 file changed, 13 insertions(+), 22 deletions(-)
diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c
index 0caf5ca1fc07..97e595238a8c 100644
--- a/drivers/acpi/ec.c
+++ b/drivers/acpi/ec.c
@@ -372,23 +372,6 @@ static inline void acpi_ec_disable_gpe(struct acpi_ec *ec, bool close)
}
}
-static inline void acpi_ec_clear_gpe(struct acpi_ec *ec)
-{
- /*
- * GPE STS is a W1C register, which means:
- * 1. Software can clear it without worrying about clearing other
- * GPEs' STS bits when the hardware sets them in parallel.
- * 2. As long as software can ensure only clearing it when it is
- * set, hardware won't set it in parallel.
- * So software can clear GPE in any contexts.
- * Warning: do not move the check into advance_transaction() as the
- * EC commands will be sent without GPE raised.
- */
- if (!acpi_ec_is_gpe_raised(ec))
- return;
- acpi_clear_gpe(NULL, ec->gpe);
-}
-
/* --------------------------------------------------------------------------
* Transaction Management
* -------------------------------------------------------------------------- */
@@ -639,13 +622,21 @@ static void advance_transaction(struct acpi_ec *ec, bool interrupt)
bool wakeup = false;
ec_dbg_stm("%s (%d)", interrupt ? "IRQ" : "TASK", smp_processor_id());
+
/*
- * By always clearing STS before handling all indications, we can
- * ensure a hardware STS 0->1 change after this clearing can always
- * trigger a GPE interrupt.
+ * Clear GPE_STS upfront to allow subsequent hardware GPE_STS 0->1
+ * changes to always trigger a GPE interrupt.
+ *
+ * GPE STS is a W1C register, which means:
+ *
+ * 1. Software can clear it without worrying about clearing the other
+ * GPEs' STS bits when the hardware sets them in parallel.
+ *
+ * 2. As long as software can ensure only clearing it when it is set,
+ * hardware won't set it in parallel.
*/
- if (ec->gpe >= 0)
- acpi_ec_clear_gpe(ec);
+ if (ec->gpe >= 0 && acpi_ec_is_gpe_raised(ec))
+ acpi_clear_gpe(NULL, ec->gpe);
status = acpi_ec_read_status(ec);
t = ec->curr;
--
2.26.2
next prev parent reply other threads:[~2020-11-23 19:41 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-23 19:35 [PATCH 0/5] ACPI: EC: Cleanups in advance_transaction() Rafael J. Wysocki
2020-11-23 19:37 ` Rafael J. Wysocki [this message]
2020-11-23 19:37 ` [PATCH 2/5] ACPI: EC: Rename acpi_ec_is_gpe_raised() Rafael J. Wysocki
2020-11-23 19:38 ` [PATCH 3/5] ACPI: EC: Simplify error handling in advance_transaction() Rafael J. Wysocki
2020-11-23 19:39 ` [PATCH 4/5] ACPI: EC: Untangle " Rafael J. Wysocki
2020-11-23 19:40 ` [PATCH 5/5] ACPI: EC: Clean up status flags checks " Rafael J. Wysocki
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