From: Lu Baolu <baolu.lu@linux.intel.com>
To: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
Tom Murphy <murphyt7@tcd.ie>,
David Woodhouse <dwmw2@infradead.org>,
Christoph Hellwig <hch@infradead.org>
Cc: Ashok Raj <ashok.raj@intel.com>,
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
Lu Baolu <baolu.lu@linux.intel.com>,
Logan Gunthorpe <logang@deltatee.com>
Subject: [PATCH v6 5/7] iommu/vt-d: Update domain geometry in iommu_ops.at(de)tach_dev
Date: Tue, 24 Nov 2020 16:20:55 +0800 [thread overview]
Message-ID: <20201124082057.2614359-6-baolu.lu@linux.intel.com> (raw)
In-Reply-To: <20201124082057.2614359-1-baolu.lu@linux.intel.com>
The iommu-dma constrains IOVA allocation based on the domain geometry
that the driver reports. Update domain geometry everytime a domain is
attached to or detached from a device.
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Tested-by: Logan Gunthorpe <logang@deltatee.com>
---
drivers/iommu/intel/iommu.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 414b4321fb61..5f7d8148f1d6 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -67,8 +67,8 @@
#define MAX_AGAW_WIDTH 64
#define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)
-#define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
-#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)
+#define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << ((gaw) - VTD_PAGE_SHIFT)) - 1)
+#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << (gaw)) - 1)
/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
to match. That way, we can use 'unsigned long' for PFNs with impunity. */
@@ -739,6 +739,18 @@ static void domain_update_iommu_cap(struct dmar_domain *domain)
*/
if (domain->nid == NUMA_NO_NODE)
domain->nid = domain_update_device_node(domain);
+
+ /*
+ * First-level translation restricts the input-address to a
+ * canonical address (i.e., address bits 63:N have the same
+ * value as address bit [N-1], where N is 48-bits with 4-level
+ * paging and 57-bits with 5-level paging). Hence, skip bit
+ * [N-1].
+ */
+ if (domain_use_first_level(domain))
+ domain->domain.geometry.aperture_end = __DOMAIN_MAX_ADDR(domain->gaw - 1);
+ else
+ domain->domain.geometry.aperture_end = __DOMAIN_MAX_ADDR(domain->gaw);
}
struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus,
--
2.25.1
next prev parent reply other threads:[~2020-11-24 8:28 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-24 8:20 [PATCH v6 0/7] Convert the intel iommu driver to the dma-iommu api Lu Baolu
2020-11-24 8:20 ` [PATCH v6 1/7] iommu: Handle freelists when using deferred flushing in iommu drivers Lu Baolu
2020-11-24 8:20 ` [PATCH v6 2/7] iommu: Add iommu_dma_free_cpu_cached_iovas() Lu Baolu
2020-11-24 8:20 ` [PATCH v6 3/7] iommu: Allow the dma-iommu api to use bounce buffers Lu Baolu
2020-11-24 8:20 ` [PATCH v6 4/7] iommu: Add quirk for Intel graphic devices in map_sg Lu Baolu
2020-11-24 8:20 ` Lu Baolu [this message]
2020-11-24 8:20 ` [PATCH v6 6/7] iommu/vt-d: Convert intel iommu driver to the iommu ops Lu Baolu
2020-11-24 8:20 ` [PATCH v6 7/7] iommu/vt-d: Cleanup after converting to dma-iommu ops Lu Baolu
2020-11-25 14:05 ` [PATCH v6 0/7] Convert the intel iommu driver to the dma-iommu api Will Deacon
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