From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Joerg Roedel <joro@8bytes.org>,
Jordan Crouse <jcrouse@codeaurora.org>,
Rob Clark <robdclark@gmail.com>
Cc: Akhil P Oommen <akhilpo@codeaurora.org>,
freedreno@lists.freedesktop.org,
Kristian H Kristensen <hoegsberg@google.com>,
dri-devel@lists.freedesktop.org,
iommu@lists.linux-foundation.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Subject: [PATCHv10 1/9] iommu/io-pgtable: Add a domain attribute for pagetable configuration
Date: Wed, 25 Nov 2020 12:30:10 +0530 [thread overview]
Message-ID: <9190aa16f378fc0a7f8e57b2b9f60b033e7eeb4f.1606287059.git.saiprakash.ranjan@codeaurora.org> (raw)
In-Reply-To: <cover.1606287059.git.saiprakash.ranjan@codeaurora.org>
Add a new iommu domain attribute DOMAIN_ATTR_IO_PGTABLE_CFG
for pagetable configuration which initially will be used to
set quirks like for system cache aka last level cache to be
used by client drivers like GPU to set right attributes for
caching the hardware pagetables into the system cache and
later can be extended to include other page table configuration
data.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
include/linux/io-pgtable.h | 4 ++++
include/linux/iommu.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h
index 4cde111e425b..215fd9d69540 100644
--- a/include/linux/io-pgtable.h
+++ b/include/linux/io-pgtable.h
@@ -208,6 +208,10 @@ struct io_pgtable {
#define io_pgtable_ops_to_pgtable(x) container_of((x), struct io_pgtable, ops)
+struct io_pgtable_domain_attr {
+ unsigned long quirks;
+};
+
static inline void io_pgtable_tlb_flush_all(struct io_pgtable *iop)
{
iop->cfg.tlb->tlb_flush_all(iop->cookie);
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index b95a6f8db6ff..ffaa389ea128 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -118,6 +118,7 @@ enum iommu_attr {
DOMAIN_ATTR_FSL_PAMUV1,
DOMAIN_ATTR_NESTING, /* two stages of translation */
DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE,
+ DOMAIN_ATTR_IO_PGTABLE_CFG,
DOMAIN_ATTR_MAX,
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2020-11-25 7:01 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-25 7:00 [PATCHv10 0/9] System Cache support for GPU and required SMMU support Sai Prakash Ranjan
2020-11-25 7:00 ` Sai Prakash Ranjan [this message]
2020-11-25 7:00 ` [PATCHv10 2/9] iommu/io-pgtable-arm: Add support to use system cache Sai Prakash Ranjan
2020-11-25 7:00 ` [PATCHv10 3/9] iommu/arm-smmu: Add support for pagetable config domain attribute Sai Prakash Ranjan
2020-11-25 7:00 ` [PATCHv10 4/9] iommu/arm-smmu: Move non-strict mode to use io_pgtable_domain_attr Sai Prakash Ranjan
2020-11-25 7:00 ` [PATCHv10 5/9] drm/msm: rearrange the gpu_rmw() function Sai Prakash Ranjan
2020-11-25 7:00 ` [PATCHv10 6/9] drm/msm/a6xx: Add support for using system cache(LLC) Sai Prakash Ranjan
2020-11-25 7:00 ` [PATCHv10 7/9] drm/msm/a6xx: Add support for using system cache on MMU500 based targets Sai Prakash Ranjan
2020-11-25 7:00 ` [PATCHv10 8/9] iommu: arm-smmu-impl: Use table to list QCOM implementations Sai Prakash Ranjan
2020-11-25 7:00 ` [PATCHv10 9/9] iommu: arm-smmu-impl: Add a space before open parenthesis Sai Prakash Ranjan
2020-11-25 14:05 ` [PATCHv10 0/9] System Cache support for GPU and required SMMU support Will Deacon
2020-11-25 14:05 ` Will Deacon
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