From: "周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>
To: sboyd@kernel.org, robh+dt@kernel.org, mturquette@baylibre.com,
paul@crapouillou.net
Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, dongsheng.qiu@ingenic.com,
aric.pzqi@ingenic.com, rick.tyliu@ingenic.com,
yanfei.li@ingenic.com, sernia.zhou@foxmail.com,
zhenwenjin@gmail.com
Subject: [PATCH 1/4] clk: JZ4780: Add function for disable the second core.
Date: Thu, 26 Nov 2020 01:26:15 +0800 [thread overview]
Message-ID: <20201125172618.112707-2-zhouyanjie@wanyeetech.com> (raw)
In-Reply-To: <20201125172618.112707-1-zhouyanjie@wanyeetech.com>
Add "jz4780_core1_disable()" for disable the second core of JZ4780,
prepare for later commits.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
drivers/clk/ingenic/jz4780-cgu.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
index 0268d23..dcca74e 100644
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -252,8 +252,29 @@ static int jz4780_core1_enable(struct clk_hw *hw)
return 0;
}
+static void jz4780_core1_disable(struct clk_hw *hw)
+{
+ struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
+ struct ingenic_cgu *cgu = ingenic_clk->cgu;
+ unsigned long flags;
+ u32 lcr, clkgr1;
+
+ spin_lock_irqsave(&cgu->lock, flags);
+
+ lcr = readl(cgu->base + CGU_REG_LCR);
+ lcr |= LCR_PD_SCPU;
+ writel(lcr, cgu->base + CGU_REG_LCR);
+
+ clkgr1 = readl(cgu->base + CGU_REG_CLKGR1);
+ clkgr1 |= CLKGR1_CORE1;
+ writel(clkgr1, cgu->base + CGU_REG_CLKGR1);
+
+ spin_unlock_irqrestore(&cgu->lock, flags);
+}
+
static const struct clk_ops jz4780_core1_ops = {
.enable = jz4780_core1_enable,
+ .disable = jz4780_core1_disable,
};
static const s8 pll_od_encoding[16] = {
--
2.7.4
next prev parent reply other threads:[~2020-11-25 17:27 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-25 17:26 [PATCH 0/4] Add new clocks for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2020-11-25 17:26 ` 周琰杰 (Zhou Yanjie) [this message]
2020-12-02 22:21 ` [PATCH 1/4] clk: JZ4780: Add function for disable the second core Paul Cercueil
2020-11-25 17:26 ` [PATCH 2/4] dt-bindings: clock: Add missing clocks for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2020-12-02 22:19 ` Paul Cercueil
2020-12-08 16:05 ` Rob Herring
2020-11-25 17:26 ` [PATCH 3/4] clk: Ingenic: " 周琰杰 (Zhou Yanjie)
2020-12-02 22:18 ` Paul Cercueil
2020-12-05 15:11 ` Zhou Yanjie
2020-11-25 17:26 ` [PATCH 4/4] clk: Ingenic: Fill unused bits in parents and reformat code 周琰杰 (Zhou Yanjie)
2020-12-02 22:09 ` Paul Cercueil
2020-12-05 14:53 ` Zhou Yanjie
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